Modeling and Design of Polythiophene Gate Electrode ChemFETs for Environmental Pollutant Sensing

Water-borne pollutants such as volatile organic compounds are a serious environmental concern, which has increased the demand for chemical sensing elements. Solidstate sensors based on catalytic gate devices are a subject of current research, however they are restricted in practical applications because of their inability to operate at room temperature. Conducting polymer FETs, which employ a conducting gate polymer, have received much attention due to their unique electronic and optical properties. Polythiophene is chosen as the semi-conductive gate polymer in this work. A functional group attached to the polythiophene is used to detect analytes (i.e., mercury in this work) of interest. The selectivity of the derivitized polythiophene to mercury can he rationalized based on the size of the ring, presence of oxygen and nitrogen donor atoms. In this paper, the modeling and design of a polythiophene gate electrode ChemFET will he discussed. Specifically the model development and resultant device simulations using Silvaco TCAD will be presented. Using this model various current-voltage characteristics of the ChemFET corresponding to parameters such as substrate doping, gate oxide thickness, various gate stacks, and device geometries are presented

Pattern Alignment Effects in Through-Wafer Bulk Micromachining of (100) Silicon

Precise alignment of the mask patterns relative to wafer crystallographic orientation is critical in the fabrication of many MEMS devices. Slight misalignment between the two can create striations and other defects in the etched sidewalls using an orientation dependent etchant such as potassium hydroxide (KOH). This paper focuses on the characterization of the resultant geometries due to the deliberate misalignment of photolithographically defined patterns relative to the (110) plane in (100) orientation silicon. The surface roughness of the etched (111) sidewall are characterized using optical microscopy, scanning electron microscopy and profilometry

Fiscal Year 1999

This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds

Process Development of Electron Beam Lithography in an Academic Environment

This paper compares the processes of photolithography and electron beam lithography (EBL). In addition, we discuss the procedure used to implement EBL in a university laboratory, specifically Boise State University’s (BSU) Idaho Microfabrication Laboratory (IML)

Focused ion beam damage to MOS integrated circuits

Commercial focused ion beam (FIB) systems are commonly used to image integrated circuits (ICS) after device processing, especially in failure analysis applications. FIB systems are also often employed to repair faults in metal lines for otherwise functioning ICS, and are being evaluated for applications in film deposition and nanofabrication. A problem that is often seen in FIB imaging and repair is that ICS can be damaged during the exposure process. This can result in degraded response or out-right circuit failure. Because FIB processes typically require the surface of an IC to be exposed to an intense beam of 30--50 keV Ga{sup +} ions, both charging and secondary radiation damage are potential concerns. In previous studies, both types of effects have been suggested as possible causes of device degradation, depending on the type of device examined and/or the bias conditions. Understanding the causes of this damage is important for ICS that are imaged or repaired by a FIB between manufacture and operation, since the performance and reliability of a given IC is otherwise at risk in subsequent system application. In this summary, the authors discuss the relative roles of radiation damage and charging effects during FIB imaging. Data from exposures of packaged parts under controlled bias indicate the possibility for secondary radiation damage during FIB exposure. On the other hand, FIB exposure of unbiased wafers (a more common application) typically results in damage caused by high-voltage stress or electrostatic discharge. Implications for FIB exposure and subsequent IC use are discussed

Focused Ion Beam Induced Effects on MOS Transistor Parameters

We report on recent studies of the effects of 50 keV focused ion beam (FIB) exposure on MOS transistors. We demonstrate that the changes in value of transistor parameters (such as threshold voltage, V{sub t}) are essentially the same for exposure to a Ga+ ion beam at 30 and 50 keV under the same exposure conditions. We characterize the effects of FIB exposure on test transistors fabricated in both 0.5 {micro}m and 0.225 {micro}m technologies from two different vendors. We report on the effectiveness of overlying metal layers in screening MOS transistors from FIB-induced damage and examine the importance of ion dose rate and the physical dimensions of the exposed area