A 2.7-kW, 29-MHz class-E/F/sub odd/ amplifier with a distributed active transformer

A Class-E/Fodd high power amplifier (PA) using the distributed active transformer (DAT) is demonstrated at 29MHz. The DAT combines the output power from four VDMOS push-pull pairs. The zero voltage switching (ZVS) condition is investigated and modified for the Class-E/Fodd amplifier with a non-ideal output transformer. All lumped elements including the DAT and the transistor package are modeled and optimized to achieve the ZVS condition and the high drain efficiency. The PA exhibits 2.7kW output power with 79% drain efficiency and 18dB gain at 29MHz

Analysis and elimination of hysteresis and noisy precursors in power amplifiers

Power amplifiers (PAs) often exhibit instabilities leading to frequency division by two or oscillations at incommensurate frequencies. This undesired behavior can be detected through a large-signal stability analysis of the solution. However, other commonly observed phenomena are still difficult to predict and eliminate. In this paper, the anomalous behavior observed in a Class-E PA is analyzed in detail. It involves hysteresis in the power-transfer curve, oscillation, and noisy precursors. The precursors are pronounced bumps in the power spectrum due to noise amplification under a small stability margin. The correction of the amplifier performance has required the development of a new technique for the elimination of the hysteresis. Instead of a trial-and-error procedure, this technique, of general application to circuit design, makes use of bifurcation concepts to suppress the hysteresis phenomenon through a single simulation on harmonic-balance software. Another objective has been the investigation of the circuit characteristics that make the noisy precursors observable in practical circuits and a technique has been derived for their elimination from the amplifier output spectrum. All the different techniques have been experimentally validated

A 6-to-18 GHz tunable concurrent dual-band receiver front end for scalable phased arrays in 130nm CMOS

This paper presents a study and design of tunable concurrent dual-band receiver. Different system architectures and building blocks have been compared and analyzed. A tunable concurrent dual-band receiver front end has then been fabricated and characterized. It operates across a tri-tave 6-18 GHz bandwidth with a nominal 17-25 dB conversion gain, worst-case -15 dBm IIP3, and worst-case -24.5 dBm ICP 1 dB

Global stability analysis and stabilization of power amplifier

Power amplifiers often exhibit undesired behavior from certain input power value which cannot be predicted with a small-signal stability analysis. Among the commonly observed undesired phenomena are spurious oscillations, frequency divisions, hysteresis or chaos. In this contribution, simulation tools are presented, enabling an in-depth study of the origin and characteristics of these phenomena. The developed global stability analysis and stabilization tools have allowed an efficient suppression of the undesired behavior in a switching-mode power amplifier, with minimum degradation of the amplifier performance, in terms of drain efficiency and output power

Fully Integrated Frequency and Phase Generation for a 6-18GHz Tunable Multi-Band Phased-Array Receiver in CMOS

Fully integrated frequency-phase generators for a 6-18GHz wide-band phased-array receiver element are presented that generate 5-7GHz and 9-12GHz first LO signals with less than -95dBc/Hz phase noise at 100kHz offset. Second LO signals with digitally controllable fourquadrant phase- and amplitude spread with better than 3° resolution are generated and allow removal of systematic reference clock skew as well as accurate selection of the received signal phase. This frequency- and phase generation scheme was successfully demonstrated in a 6-18GHz receiver system configured as an electrical 4-element array

A tunable concurrent 6-to-18 GHz phased-array system in CMOS

This paper presents a scalable phased-array receiver system that covers a tritave bandwidth of 6-to-18 GHz implemented in a 130nm CMOS process. The single receiver element with a 10-bit phase shifting resolution achieves a maximum phase error of 2.5° within a baseband amplitude variation of 1.5dB for an arbitrary target angle. This dense interpolation provides excellent phase error/offset calibration capability in the array. A 4-element electrical array pattern is measured at 6 GHz, 13.5 GHz and 18 GHz, showing a worst case peak-to-null ratio of 21.5dB. The EVM and phase noise improvements of the array compared with the single receiver element are also shown