6 research outputs found

    Demonstration of TiO2 Based Ultra High-k (k = 30) Metal-Insulator–Semiconductor Capacitor and Its Electrical Properties

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    In this paper, we investigated TiO2 as gate dielectric to achieve the large dielectric constant. The ultra high-k value over 30 was obtained by Capacitance–Voltage measurement of Al/Ti/TiO2/Si Metal-Insulator–Semiconductor (MIS) capacitor. Among as deposited, rapid thermal annealing (RTA) at 750 °C and 1000 °C, the RTA at 750 °C showed the lowest gate leakage current. It implies that TiO2 has optimum RTA temperature having the lowest leakage current. When TiO2 is annealed at 750 °C, the phase of TiO2 changes to anatase and interfacial layer between TiOx and Si was formed. While TiO2 is annealed at 1000 °C, the phase of TiO2 changes to rutile and diffusion of silicon atoms was clearly observed and it causes the silicide formation. Based on measurement data, we proposed the energy band diagram of Al/TiO2/Si MIS capacitors. This diagram shows that the energy band gap of RTA at 750 °C is expanded while that of RTA at 1000 °C is contracted. In addition, TiO2 with RTA at 550 °C was tested to confirm leakage current and it shows lower leakage current than RTA at 750 °C as we expected. This result confirmed that optimum RTA temperature of TiO2 would exist under 750 °C.11Nsci

    H<sub>2</sub> Plasma and PMA Effects on PEALD-Al<sub>2</sub>O<sub>3</sub> Films with Different O<sub>2</sub> Plasma Exposure Times for CIS Passivation Layers

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    In this study, the electrical properties of Al2O3 film were analyzed and optimized to improve the properties of the passivation layer of CMOS image sensors (CISs). During Al2O3 deposition processing, the O2 plasma exposure time was adjusted, and H2 plasma treatment as well as post-metallization annealing (PMA) were performed as posttreatments. The flat-band voltage (Vfb) was significantly shifted (ΔVfb = 2.54 V) in the case of the Al2O3 film with a shorter O2 plasma exposure time; however, with a longer O2 plasma exposure time, Vfb was slightly shifted (ΔVfb = 0.61 V) owing to the reduction in the carbon impurity content. Additionally, the as-deposited Al2O3 sample with a shorter O2 plasma exposure time had a larger number of interface traps (interface trap density, Dit = 8.98 × 1013 eV−1·cm−2). However, Dit was reduced to 1.12 × 1012 eV−1·cm−2 by increasing the O2 plasma exposure time and further reduced after PMA. Consequently, we fabricated an Al2O3 film suitable for application as a CIS passivation layer with a reduced number of interface traps. However, the Al2O3 film with increased O2 plasma exposure time deteriorated owing to plasma damage after H2 plasma treatment, which is a method of reducing carbon impurity content. This deterioration was validated using the C–V hump and breakdown characteristics

    Cryogenic Body Bias Effect in DRAM Peripheral and Buried-Channel-Array Transistor for Quantum Computing Applications

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    This study investigated a novel forward body bias (FBB) analysis to optimize the threshold voltage ( Vth\text{V}_{\mathrm {th}} ) at cryogenic temperatures in the latest dynamic random-access memory (DRAM). Electrical measurements were conducted to analyze the cryogenic body bias effect in terms of performance, reliability, and short-channel effect in two types of transistors: DRAM peripheral low Vth\text{V}_{\mathrm {th}} transistors (Peri LVT) and buried-channel-array transistors (BCAT). At 77 K, the Vth\text{V}_{\mathrm {th}} shift ( ΔVth\Delta \text{V}_{\mathrm {th}} ) in BCAT was larger than that in Peri LVT due to the difference in channel doping concentration. It was observed that only BCAT experienced a decrease in saturation drain current ( Id.sat\text{I}_{\mathrm {d.sat}} ) at cryogenic temperature because of the large ΔVth\Delta \text{V}_{\mathrm {th}} . To compensate for the ΔVth\Delta \text{V}_{\mathrm {th}} , FBB was applied to transistors. As a result, FBB effectively controlled the Vth\text{V}_{\mathrm {th}} and improved carrier mobility. Furthermore, this study demonstrated that FBB reduced hot-carrier degradation (HCD) at cryogenic temperature and improved short-channel effect, such as drain-induced barrier lowering (DIBL). These findings offer valuable solutions for optimizing cryogenic memory operation in quantum computing applications
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