A single-input dual-output 13.56 MHz CMOS AC-DC converter with comparator-driven rectifiers for implantable devices

A highly efficient single-input, dual-output AC-DC converter for wireless power transfer in implantable devices is implemented using the 0.18-μm CMOS process. The proposed AC-DC converter, consisting of three rectifiers with cross-coupled NMOS transistors and comparator-driven PMOS transistors, achieves up to 79.5% power conversion efficiency at 13.56 MHz operation frequency in order to provide dual outputs of 1.2 V and 2.2 V DC voltages along with 6.2 mA and 22.6 mA of current, respectively, to the implant device from a single RF input. The designed IC consumes a core die area of 0.18 mm2. © 2014 Elsevier Ltd.

A Low Switching-Loss W-Band Radiometer Utilizing a Single-Pole-Double-Throw Distributed Amplifier in 0.13-mu m SiGe BiCMOS

This paper presents a low switching-loss Dicke radiometer for W-band passive imaging systems. The equivalent switching loss introduced by the passive single-pole-double-throw (SPDT) switch in the conventional radiometer is significantly reduced by the proposed single-pole-double-throw distributed amplifier (SPDT-DA), which leads to radical improvement on the receiver's noise performance. The Dicke radiometer consisting of a SPDT-DA, a four-stage low noise amplifier (LNA) and a power detector is fully integrated in a 0.13-μ SiGe BiCMOS chip. With the 0.93-dB equivalent switching loss at 91 GHz of the SPDT-DA, the total noise figure (NF) of 8.4 dB at 91 GHz is achieved by the SPDT-DA followed by the LNA. With a power consumption of 28.5 mW, the radiometer obtains an overall RF gain of 42 dB and a noise equivalent temperature difference (NETD) of 0.21 K with 30-ms integration time. The two-dimensional imaging experiment with object distance of 0.7 m is successfully carried out with the radiometer chip. © 2015 IEEE.1

Fast and energy-efficient low-voltage level shifters

This paper presents two novel low-voltage level shifter designs: one based on cross-coupled PMOS transistors and the other using current mirror structure. These two level shifters are designed to address the problems of the existing state-of-the-art level shifters. Simulation at 65 nm shows that both of the proposed level shifters achieve significantly better performance (up to 12×) and energy consumption (up to 8×) than the state-of-the-art level shifters with similar or less area consumption while operating from near-threshold to super-threshold region, making them optimal for level shifting in low-power systems with multiple scalable voltage domains. © 2014 Elsevier Ltd.

Near-Threshold Energy- and Area-Efficient Reconfigurable DWPT/DWT Processor for Healthcare-Monitoring Applications

This brief presents an energy-and area-efficient discrete wavelet packet transform (DWPT) processor design for power-constrained and cost-sensitive healthcare-monitoring applications. This DWPT processor employs recursive memory-shared architecture to achieve low hardware complexity while performing required arbitrary-basis DWPT decomposition. By exploiting inherent characteristics of different physiological signals through an entropy statistic engine, the DWPT processor core can be reconfigured to compute multilevel wavelet decomposition with effective time and frequency resolution. Various design techniques from algorithm to circuit levels, including reconfigurable computing, lifting scheme, dual-port pipeline processing, near-threshold operation, and clock gating, are applied to achieve energy efficiency. With a 0.18-μ m CMOS technology at 0.5 V and 1 MHz, the DWPT core only consumes 26 μ W for performing three-level 256-point DWPT decomposition with entropy statistic calculation. When integrated in an ARM Cortex-M0-based biomedical system-on-a-chip test platform, the DWPT processor achieves processing acceleration by three orders of magnitude and reduces energy consumption by four orders of magnitude compared with CPU-only implementations. © 2015 IEEE.