Verics: A Tool for Verifying Timed Automata and Estelle Specifications

The paper presents a new tool for automated veri cation of Timed Automata as well as protocols written in the speci cation language Estelle. The current version oers an automatic translation from Estelle speci cations to timed automata, and two complementary methods of reachability analysis, the rst of which is based on Bounded Model Checking (BMC), while the second one is an on-the-y veri cation on an abstract model of the system