Future wishes and constraints from the experiments at the LHC for the Proton-Proton programme

Hosting six different experiments at four different interaction points and widely different requirements for the running conditions, the LHC machine has been faced with a long list of challenges in the first three years of luminosity production (2010-2012, Run 1), many of which were potentially capable of limiting the performance due to instabilities resulting from the extremely high bunch brightness. Nonetheless, LHC met the challenges and performed extremely well at high efficiency and routinely with beam brightness at twice the design, well over one-third of the time in collision for physics, average luminosity lifetimes in excess of 10 h and extremely good background conditions in the experiments. While the experimental running configurations remain largely the same for the future high luminosity proton-proton operational mode, the energy and the luminosity should increase significantly, making a prior assessment of related beam-beam effects extremely important to guarantee high performance. Of particular interest is the need for levelling the luminosity individually in the different experiments. Luminosity control as the more general version of 'levelling' has been at the heart of the success for LHCb, and to a large extent also for ALICE, throughout Run 1. With the increasing energy and potential luminosity, luminosity control may be required by all the experiments at some point in the future as a means of controlling the pileup conditions and trigger rates, but possibly also as a way of optimizing the integrated luminosity. This paper reviews the various motivations and possibilities for controlling the luminosity from the experiments' point of view, and outlines the future running conditions and desiderata for the experiments as they are viewed currently, with the aim of giving guidelines for different options.Comment: 10 pages, contribution to the ICFA Mini-Workshop on Beam-Beam Effects in Hadron Colliders, CERN, Geneva, Switzerland, 18-22 Mar 201

Building Integrated Remote Control Systems for Electronics Boards

This paper addresses several aspects of implementing a remote control system for a large number of electronics boards in order to perform remote Field Programmable Gate Array (FPGA) programming, hardware configuration, data register access, and monitoring, as well as interfacing it to an expert system. The paper presents a common strategy for the representation of the boards in the abstraction layer of the control system, and generic communication protocols for the access to the board resources. In addition, an implementation is proposed in which the mapping between the functional parameters and the physical registers of the different boards is represented by descriptors in the board representation such that the translation can be handled automatically by a generic translation manager. Using the Distributed Information Management (DIM) package for the control communication with the boards, and the industry SCADA system PVSS II from ETM, a complete control system has been built for the Timing and Fast Control (TFC) system of the LHCb experiment at CERN. It has been in use during the entire prototyping of the TFC system and the developments of the LHCb sub-detector electronics, and is now installed in the online system of the final experiment

Beam phase and intensity monitor (BPIM) for the LHCb Experiment

The LHC bunch clock is transmitted over kilometres of fibre to the experiments where it is distributed to thousands of front-end electronics boards. In order to ensure that the detector signals are sampled properly, its long-term stability with respect to the bunch arrival times must be monitored with a precision of <100ps. In addition it is important to monitor the trigger conditions by measuring the intensity of each bunch locally in the experiment. For this purpose, we propose a beam phase and intensity acquisition board (BPIM) for the Button Electrode Beam Pick-ups which will be installed on both sides of the LHCb interaction point. The board measures the two quantities per bunch, and processes the information in an onboard FPGA. The information is read-out by the Experiment Control System and is directly fed to the LHCb Timing and Fast Control (TFC) [1]. In the TFC system the information is included in an event data bank but may also be used as a bunch crossing trigger or gate

A 40 MHz Trigger-free Readout Architecture for the LHCb Experiment

The LHCb experiment is considering an upgrade towards a trigger-free 40 MHz complete event readout in which the event selection will only be performed on a processing farm by a high-level software trigger with access to all detector information. This would allow operating LHCb at ten times the current design luminosity and improving the trigger efficiencies in order to collect more than ten times the statistics foreseen in the first phase. In this paper we present the new architecture in consideration. In particular, we investigate new technologies and protocols for the distribution of timing and synchronous control commands, and rate control. This so called Timing and Fast Control (TFC) system will also perform a central destination control for the events and manage the load balancing of the readout network and the event filter farm. The TFC system will be centred on a single FPGA-based multimaster allowing concurrent stand-alone operation of any subset of sub-detectors. The TFC distribution network under investigation will consist of a bidirectional optical network based on the high-speed transceivers embedded in the latest generation of FPGAs with special measures to have full control of the phase and latency of the transmitted clock and information. Since data zero-suppression will be performed at the detector front-ends, the readout is effectively asynchronous and will require that the synchronous control information carry event identifiers to allow realignment and synchronization checks

A 40 MHz Trigger-free Readout Architecture for the LHCb experiment at CERN

LHCb is considering an upgrade towards a full 40 MHz readout. In this paper we investigate possibilities for a new Timing and Fast Control (TFC) system based on completely new technologies, and the consequences for the readout electronics. We define the requirements and propose an architecture allowing partitioning, complete readout control and event management. The backbone is based on bidirectional high-speed optical links using the latest FPGA transceivers. For the Front-End Electronics we advocate exploiting the bidirectional capability of the CERN GigaBit Transceiver to make the Readout Boards the TFC and the Control System interface to the Front-En

The LHCb Timing and Fast Control system

In this paper we describe the LHCb Timing and Fast Control (TFC) system. It is different from that of the other LHC experiments in that it has to support two levels of high-rate triggers. Furthermore, emphasis has been put on partitioning and on locating the TFC mastership in one type of module: the Readout Supervisor. The Readout Supervisor handles all timing, trigger, and control command distribution. It generates auto-triggers as well as controls the trigger rates. Partitioning is handled by a programmable patch panel/switch introduced in the TTC distribution network between a pool of Readout Supervisors and the Front-End electronics. I