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    22 research outputs found

    High level synthesis interconnect minimization

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    Comparison of gate sizing formulations and solving methods

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    STW Technology Foundation
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    Speed-accuracy trade-off in gate sizing

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    STW Technology Foundation
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    A path-based method for statistical delay calculation dealing with correlations due to reconverging paths.

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    Power dissipation and timing in CMOS circuits

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    Technische Universiteit Eindhoven
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    Speed-accuracy trade-off in gate sizing

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    STW Technology Foundation
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    Comparison of gate sizing formulations and solving methods

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    STW Technology Foundation
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    A continuous nonlinear constrained optimization approach for maximum power estimation for CMOS circuits

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    IEEE European Chapter, Stichting Technische Wetenschappen
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    A continuous nonlinear constrained optimization approach for maximum power estimation for CMOS circuits

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    IEEE European Chapter, Stichting Technische Wetenschappen
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    Estimation of an upper bound on the maximum power of CMOS circuits using linear programming

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    Democritus University of Thrace
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