Negative Differential Resistance in ZnO Nanowires Bridging Two Metallic Electrodes

The electrical transport through nanoscale contacts of ZnO nanowires bridging the interdigitated Au electrodes shows the negative differential resistance (NDR) effect. The NDR peaks strongly depend on the starting sweep voltage. The origin of NDR through nanoscale contacts between ZnO nanowires and metal electrodes is the electron charging and discharging of the parasitic capacitor due to the weak contact, rather than the conventional resonant tunneling mechanism

Performances of Soi Cmos Ota Combining Ztc and Gain-boosting Techniques

A folded-cascode CMOS FD SOI OTA with a gain-boosting stage has been designed using the ZTC concept. The measured room-temperature 115dB DC gain for a 113MHz transition frequency outperforms all previous SOI or bulk opamp performances. High-temperature measurements up to 400 degrees C are reported for the first time

Effects of Total-dose Irradiation On Gate-all-around (gaa) Devices

The response of Gate-All-Around MOS transistors to dose irradiation is quite different from that observed on other types of Silicon-On-Insulator MOSFETs. Indeed, in regular SOI MOSFETs, edge leakage increases substantially faster than the main transistor leakage upon creation of oxide charges due to the irradiation. The GAA MOSFET behaves in the opposite way: the shift of edge threshold voltage upon creation of charges in the oxide is smaller than that of the main transistor. As a result, a kink develops in the subthreshold characteristics of regular SOI MOSFETs upon irradiation, while the original subthreshold kink of GAA devices disappears when the device is irradiated

Two-dimensional confinement effects in gate-all-around (GAA) MOSFETS

Two-dimensional electron confinement effects have been modeled and experimentally observed in silicon-on-insulator (SOI) gate-all-around (GAA) MOSFETs. Solving the Poisson and Schrodinger equations in a self-consistent manner provides the electron wave functions and the energy levels within the device channel. The variation of these energy levels, as well as the electron concentration profile, have been computed as a function of gate voltage. Transconductance fluctuations are observed as new energy levels become populated. (C) 1998 Elsevier Science Ltd. All rights reserved

Fabrication of twin nano silicon wires based on arsenic dopant effect

This paper reports a simple fabrication process of Si "twin nano wires" based on As dopant effect which gives rise to a significant increase of the oxidation rate at the peak concentration of As. The processing procedures consist of As doping, deposition of silicon nitride layer, electron beam lithography, reactive ion etching, wet oxide and deposition of polysilicon. The resulting Si "twin nano wires': have a small top wire with a dimension of 10 nm and a triangular channel wire with a height of 250 nm. A possible application of the "twin nano wires" to a future single-electron memory device on silicon on insulator (SOI) wafer is also discussed

Substrate influences on fully depleted enhancement mode SOI MOSFETs at room temperature and at 77 K

In this work a theoretical and experimental analysis is presented of the substrate potential drop influence on fully depleted enhancement mode silicon-on-insulator (SOI) MOSFETs. The theoretical results are compared with MEDICI numerical bidimensional simulations in order to validate the proposed model. The substrate influence on the SOI MOSFET threshold voltage and sub-threshold slope is studied. Finally, a comparison between modeled and experimental results is realized and a good agreement is found. Copyright (C) 1996 Elsevier Science Lt

Comparison of self-heating effect in GAA and SOI mosfets

An analytical model is developed to estimate the effect of the scaling of the buried oxide on the heat flow in SOI devices. The heat evacuation is shown to follow the buried oxide thickness to the n-th power with -0.5 > n > -1, and it strongly depends on device dimensions. Three experimental independent evidences of reduced self-heating in GAA devices are provided and analyzed in the light of an analytical model. The advantage of the GAA structure is to replace the buried oxide below the channel by a back polysilicon gate that benefits for a much larger thermal conductivity. To achieve the same result in SOI devices, the buried oxide thickness should be reduced down to twice the gate oxide thickness, which unfortunately would also lead to a dramatic increase of source and drain parasitic capacitances. In the GAA transistor, on the contrary, source and drain regions still lie on the thick buried oxide layer such that those parasitic elements keep a low value