Hierarchy Exploration in High Level Memory Management

Introducing an optimized memory hierarchy to exploit temporal locality in the memory accesses on array signals can have a very large impact on the power consumption in data dominated applications. In this paper the design freedom available for the basic problem is explored in-depth and the outline of a systematic solution methodology is proposed. The methodology is illustrated on a real-life motion estimation application. The results obtained for this application show power reductions of about 85% for the memory sub-system compared to the case without memory hierarchy. These large gains justify that memory hierarchy design should be done early in the global memory management script. 1 Introduction The idea of using memory hierarchy to minimize the power consumption, is based on the fact that memory power consumption depends primarily on the access frequency and the size of the memory. Power savings can be obtained by accessing heavily used data from smaller memories instead of from la..