Energy Model of Networks-on-Chip and a Bus

A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both NoC architectures to predict their energy consumption per transported bit. Both architectures are also compared with a traditional bus architecture. The energy model is primarily needed to find a near optimal run-time mapping (from an energy point of view) of inter-process communication to NoC link

An Approximate Maximum Common Subgraph Algorithm for Large Digital Circuits

This paper presents an approximate Maximum Common Subgraph (MCS) algorithm, specifically for directed, cyclic graphs representing digital circuits. \ud Because of the application domain, the graphs have nice properties: they are very sparse; have many different labels; and most vertices have only one predecessor. The algorithm iterates over all vertices once and uses heuristics to find the MCS. It is linear in computational complexity with respect to the size of the graph. Experiments show that very large common subgraphs were found in graphs of up to 200,000 vertices within a few minutes, when a quarter or less of the graphs differ. The variation in run-time and quality of the result is low

Energy-Efficient NoC for Best-Effort Communication

A Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture forMulti-Processor System-on-Chip (MPSoC) architectures. In an earlier paper we proposed a energy-efficient reconfigurable circuit-switched NoC to reduce the energy consumption compared to a packetswitched NoC. In this paper we investigate a chordal slotted ring and a bus architecture that can be used to handle the best-effort traffic in the system and configure the circuitswitched network. Both architectures are compared on their latency behavior and power consumption. At the same clock frequency, the chordal ring has the major benefit of a lower latency and higher throughput. But the bus has a lower overall power consumption at the same frequency. However, if we tune the frequency of the network to meet the throughput requirements of control network, we see that the ring consumes less energy per transported bit

Providing QoS Guarantees in a NoC by Virtual Channel Reservation

We propose an approach for providing Quality-of-Service guarantees in a virtual channel Network-on-Chip. The approach is based on virtual channel reservation - routes with guaranteed lower throughput bound are reserved over the virtual channels. The performance of such an approach is limited by a number of factors: number of virtual channel in the network, number of requested routes, traffic locality etc. We test the performance of the proposed approach for variety of traffic conditions. We investigate the influence of three system parameters - routing algorithm, network topology and communication locality - on the performance limits of the approach. The results are derived by simulations using a streaming traffic model. The results show the approach is feasible for a network of size 10-by-10 with four virtual channels per physical channel. The traffic locality has strong influence on the performance limits of the approach and can also help in reducing the communication energy cost by 50% to 70%. The type of the routing algorithm does not practically influence the performance limits

An Energy-Efficient Reconfigurable Circuit Switched Network-on-Chip

Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture for multi-tile System-on-Chip (SoC) architectures. The SoC architecture, including its run-time software, can replace inflexible ASICs for future ambient systems. These ambient systems have to be flexible as well as energy-efficient. To find an energy-efficient solution for the communication network we analyze three wireless applications. Based on their communication requirements we observe that revisiting of the circuit switching techniques is beneficial. In this paper we propose a new energy-efficient reconfigurable circuit-switched Network-on-Chip. By physically separating the concurrent data streams we reduce the overall energy consumption. The circuit-switched router has been synthesized and analyzed for its power consumption in 0.13 ¿m technology. A 5-port circuit-switched router has an area of 0.05 mm2 and runs at 1075 MHz. The proposed architecture consumes 3.5 times less energy compared to its packet-switched equivalen

Surprising phenomena in a rich new class of inflationary models

We report on a new class of fast-roll inflationary models. In a huge part of its parameter space, inflationary perturbations exhibit quite unusual phenomena such as scalar and tensor modes freezing out at widely different times, as well as scalar modes reentering the horizon during inflation. In another, narrower range of parameters, this class of models agrees with observations. One specific point in parameter space is characterized by extraordinary behavior of the scalar perturbations. Freeze-out of scalar perturbations as well as particle production at horizon crossing are absent. Also the behavior of the perturbations around this quasi-de Sitter background is dual to a quantum field theory in flat space-time. Finally, the form of the primordial power spectrum is determined by the interaction between different modes of scalar perturbations.Comment: 12 pages, 5 figures, 1 table, references + comments added, errors corrected, conclusions unchanged, version published in JCA

The Chameleon Architecture for Streaming DSP Applications

We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm$^2$ in a 130 nm process), is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC) via a network interface (NI). Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT) and best effort (BE). For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool

Scaling law of Wolff cluster surface energy

We study the scaling properties of the clusters grown by the Wolff algorithm on seven different Sierpinski-type fractals of Hausdorff dimension $1 < d_f \le 3$ in the framework of the Ising model. The mean absolute value of the surface energy of Wolff cluster follows a power law with respect to the lattice size. Moreover, we investigate the probability density distribution of the surface energy of Wolff cluster and are able to establish a new scaling relation. It enables us to introduce a new exponent associated to the surface energy of Wolff cluster. Finally, this new exponent is linked to a dynamical exponent via an inequality.Comment: 12 pages, 3 figures. To appear in PR