Design, construction and commissioning of a technological prototype of a highly granular SiPM-on-tile scintillator-steel hadronic calorimeter

The CALICE collaboration is developing highly granular electromagnetic and hadronic calorimeters for detectors at future energy frontier electron-positron colliders. After successful tests of a physics prototype, a technological prototype of the Analog Hadron Calorimeter has been built, based on a design and construction techniques scalable to a collider detector. The prototype consists of a steel absorber structure and active layers of small scintillator tiles that are individually read out by directly coupled SiPMs. Each layer has an active area of 72 × 72 cm^2 and a tile size of 3 × 3 cm^2. With 38 active layers, the prototype has nearly 22,000 readout channels, and its total thickness amounts to 4.4 nuclear interaction lengths. The dedicated readout electronics provide time stamping of each hit with an expected resolution of about 1 ns. The prototype was constructed in 2017 and commissioned in beam tests at DESY. It recorded muons, hadron showers and electron showers at different energies in test beams at CERN in 2018. In this paper, the design of the prototype, its construction and commissioning are described. The methods used to calibrate the detector are detailed, and the performance achieved in terms of uniformity and stability is presented

CALICE SiW ECAL - Development and performance of a highly compact digital readout system

International audienceA highly granular silicon-tungsten electromagnetic calorimeter (SiW-ECAL) is thereference design of the ECAL of the International Large Detector (ILD) concept, one of the twodetector concepts for the detector(s) at the future International Linear Collider. Prototypes for thistype of detector are developed within the CALICE Collaboration. During the last year a highlycompact digital readout system has been built. The system has been used for the first time in a beamtest in Summer 2019 at DESY. This article summarises the main features of the system and reporton its performance during the beam test

LSST camera readout chip ASPIC: test tools

Open AccessInternational audienceThe LSST camera will have more than 3000 video-processing channels. The readout of this large focal plane requires a very compact readout chain. The correlated ''Double Sampling technique'', which is generally used for the signal readout of CCDs, is also adopted for this application and implemented with the so called ''Dual Slope integrator'' method. We have designed and implemented an ASIC for LSST: the Analog Signal Processing asIC (ASPIC). The goal is to amplify the signal close to the output, in order to maximize signal to noise ratio, and to send differential outputs to the digitization. Others requirements are that each chip should process the output of half a CCD, that is 8 channels and should operate at 173 K. A specific Back End board has been designed especially for lab test purposes. It manages the clock signals, digitizes the analog differentials outputs of ASPIC and stores data into a memory. It contains 8 ADCs (18 bits), 512 kwords memory and an USB interface. An FPGA manages all signals from/to all components on board and generates the timing sequence for ASPIC. Its firmware is written in Verilog and VHDL languages. Internals registers permit to define various tests parameters of the ASPIC. A Labview GUI allows to load or update these registers and to check a proper operation. Several series of tests, including linearity, noise and crosstalk, have been performed over the past year to characterize the ASPIC at room and cold temperature. At present, the ASPIC, Back-End board and CCD detectors are being integrated to perform a characterization of the whole readout chain

ASPIC and CABAC: two ASICs to readout and pilot CCD

International audienceFor several years, a group of engineers and physicists from LAL and LPNHE have been working on the design of two front end ASICs dedicated to Charge Couple Devices (CCD). ASPIC (Analogue Signal Processing Integrated Circuit), designed in AMS CMOS 0.35 μm 5V technology, is meant to readout and process the analog signals of CCDs. CABAC (Clocks And Biases ASIC for CCDs), designed in AMS CMOS 0.35 μm 50V technology, produces the clocks and biases needed by the CCDs to work at their full potential. This paper presents the performances of the final versions of these two ASICs

ASPIC: LSST camera readout chip. Comparison between DSI and C&S

Main authors : V. Tocut ; H. LebboloThe LSST camera will have more than 3000 video-processing channels to readout its large and highly segmented focal plane, requiring a compact readout chain. The standard technique for analog signal processing of CCDs is “Correlated Double Sampling,” which can be implemented with “Dual Slope Integrator” or “Clamp and Sample” methods. We have designed and implemented an ASIC for LSST to directly compare the strengths and weaknesses of these methods on a working device: the Analog Signal Processing asIC (ASPIC). Four channels of each method have been implemented on the same ASIC to perform direct comparisons and fine crosstalk measurements. Video channel to video channel crosstalk due to electronics (cables, boards, chips) has to be no more than 0.05% (1::2000) with a 0.01% goal (1::10000) at 500kHz readout frequency. The other requirements on this readout chain are: - readout noise < 7µV rms for an integration time of 500ns - crosstalk < 0.05% - linearity < 1% - dynamic range 16 bits - maximum power consumption of 25mW/channel - working temperature 173 K - differential ouputs driving 1kΩ // 50pF load The chosen technology is 5V compliant CMOS 0,35µ by AMS. A second version, ASPIC 2, containing 8 DSI channels has been submitted by the end of 2008. This version is characterized by a 3 bit programmable gain (made by capacitive feedback) of the input amplifier, and a 3 bit programmable time constant integrator in order to match the CCD output conversion and the readout frequency. In order to reduce the power consumption, an idle mode has been implemented. First measurements show an important improvement in noise which has been reduced to less than 7µV for an integration time of 500ns at room temperature. Power consumption is now around 26mW/ch also at room temperature. A very preliminary crosstalk of 0.02% has been measured on a socket mounted chip. A CLAmp and Sample aSIC (CLASSIC) chip containing 8 channels has been submitted in march in order to perform a comparison between the two methods. CLASSIC is also characterized by a programmable input amplifiers gain and a programmable time constant output filter

Cherenkov detector for proton flux measurement for UA9 project

A report about the development of a device called Cherenkov detector for proton flux measurement is presented. This device is going to be installed first in the Super Proton Synchrotron and later at Large Hadron Collider collimation area to monitor of the secondary beam, produced by a bent crystal inserted in the proton halo. By measuring the number of Cherenkov light produced by the protons in the quartz radiator we expect less the 10% precision in particle counting, for around 100 incoming protons. Geant4 based simulation and first tests with 446 MeV electron beam are discussed. © 2013 IEEE