High-frequency two-input CMOS OTA for continuous-time filter applications

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”A high-frequency fully differential CMOS operational transconductance amplifier (OTA) is presented for continuous-time filter applications in the megahertz range. The proposed design technique combines a linear cross-coupled quad input stage with an enhanced folded-cascode circuit to increase the output resistance of the amplifier. SPICE simulations show that DC-gain enhancement can be obtained without significant bandwidth limitation. The two-input OTA developed is used in high-frequency tuneable filter design based on IFLF and LC ladder simulation structures. Simulated results of parameters and characteristics of the OTA and filters in a standard 1.2 μm CMOS process (MOSIS) are presented. A tuning circuit is also discussed.Peer reviewe

Automatic tuning of a resonant circuit in wireless power supply systems for biomedical sensors

In this paper, a tuning method of a resonant circuit suited for wireless powering of miniature endoscopic capsules is presented and discussed. The method allows for an automatic tuning of the resonant frequency and matching impedance of a full wave rectifier loading the resonant circuit. Thereby, the receiver tunes so as to obtain the highest power efficiency under given conditions of transmission. A prototype receiver for wireless power reception, fabricated in in AMS CMOS 0.35 μm technology, was used to verify correct operation of the proposed tuning. The prototype system produces a stable supply voltage, adjustable in the range of 1.2–1.8 V at a maximum output current of 100–67 mA, which is sufficient to power a typical endoscopic capsule

CMOS implementation of an analogue median filter for image processing in real time

An analogue median filter, realised in a 0.35 μm CMOS technology, is presented in this paper. The key advantages of the filter are: high speed of image processing (50 frames per second), low-power operation (below 1.25 mW under 3.3 V supply) and relatively high accuracy of signal processing. The presented filter is a part of an integrated circuit for image processing (a vision chip), containing: a photo-sensor matrix, a set of analogue pre-processors, and interface circuits. The analysis of the main parameters of the considered median filter is presented. The discussion of important limitations in the operation of the filter due to the restrictions imposed by CMOS technology is also presented

A High-Efficient Low-Voltage Rectifier for CMOS Technology

A new configuration of rectifier suiting CMOS technology is presented. The rectifier consists of only two n-channel MOS transistors, two capacitors and two resistors; for this reason it is very favourable in manufacturing in CMOS technology. With these features the rectifier is easy to design and cheap in production. Despite its simplicity, the rectifier has relatively good characteristics, the voltage and power efficiency, and bandwidth greater than 89%, 87%, and 1 GHz, respectively. The performed simulations and measurements of a prototype circuit fully confirmed its correct operation and advantages

Characteristics of an image sensor with early-vision processing fabricated in standard 0.35 žm CMOS technology

The article presents measurement results of prototype integrated circuits for acquisition and processing of images in real time. In order to verify a new concept of circuit solutions of analogue image processors, experimental integrated circuits were fabricated. The integrated circuits, designed in a standard 0.35 žm CMOS technology, contain the image sensor and analogue processors that perform low-level convolution-based image processing algorithms. The prototype with a resolution of 32 x 32 pixels allows the acquisition and processing of images at high speed, up to 2000 frames/s. Operation of the prototypes was verified in practice using the developed software and a measurement system based on a FPGA platform

CMOS realisation of analogue processor for early vision processing

The architecture concept of a high-speed low-power analogue vision chip, which performs low-level real-time image algorithms is presented. The proof-of-concept prototype vision chip containing 32 �~ 32 photosensor array and 32 analogue processors is fabricated using a 0.35 mikrom CMOS technology. The prototype can be configured to register and process images with very high speed, reaching 2000 frames per second, or achieve very low power consumption, several mikroW. Finally, the experimental results are presented and discussed

Surface-to-air missile system "SA-6" modernization

W artykule przedstawiono projekt modernizacji przeciwlotniczego zestawu rakietowego KUB mający na celu, w oparciu o radar z anteną bezinercyjną, zmianę sposobu realizacji procedur i metod wykrywania celu oraz określania parametrów startowych rakiety i sposobu naprowadzania rakiety na cel.In this article presents guidelines of surface-to-air missilc system "SA-6" modernization based on electronically steered antenna (KSA) radar utilisation. The paper describes modernization improvements connected with targets acquisition and tracking, missile guidance/homing and benefins deal with system association