Heterogeneous Integration and Fabrication of III-V MOS Devices in a 200mm Processing Environment

We report on the fabrication of MOS capacitors on 200 mm virtual GaAs substrates using a Si CMOS processing environment. The fabricated capacitors were comparable to those processed on bulk GaAs material. Topside contact was made to the GaAs using a novel CMOS compatible self-aligned NiGe contact scheme resulting in a measured contact resistance of 0.26 [ohm sign].cm. Cross-contamination from various III-V substrates was investigated and it was found that by limiting the thermal budget to <= 300C cross-contamination from the outgassing of In, Ga and As could be eliminated. For wet processing the judicious choice of recipe and processing conditions resulted in no significant cross-contamination being detected as determined by TXRF monitoring. This achievement enables III-V device production using state-of-the-art Si processing equipment.Peer reviewe

Etude des propriétés électriques d empilements high-K/grille métal en vue de leur intégration dans les dispositifs CMOS-sub 45 nm

Ces travaux de recherche se concentrent autour de la caractérisation électrique des transistors MOS High-K/: métal. Tout d'abord, nous avons abordé successivement la stabilité de l'EOT correspondant à ces empilemen caractérisation 1er niveau des défauts liés à l'oxyde et l'analyse de la conduction. Ensuite, nous nous son intéressés à des défauts électriques spécifiques engendrant un phénomène particulièrement gênant, mieux 0 sous le nom de PB TI. Après la mise en place d'une technique de caractérisation innovante, notre étude m avant différentes catégories de défauts selon qu'ils sont réversibles ou non réversibles. Nous nous sommes en focalisés sur la modélisation des pièges réversibles. Les mécanismes de piégeage/ dépiégeage mis en jeu or identifiés et les caractéristiques physiques des défauts extraites. Enfin, nous avons investigué la vari incontrôlée de la tension de bande plate par le biais d'une expérience de photo-émission interne.This work concerns the study of electrical properties of advanced transistors integrating High-KImetal materials. We addressed in a first part, the basic characterization of these stacks especially EûT thermal star first-level defects characterization and conduction analysis. We are also interested in electrical defects resultin! phenomenon named Positive Bias Temperature Instability (PB TI). To make an intensive investigation of parasitic effect, we have introduced a new time resolved characterization technique evidencing different categ of PBTI defects depending on reversible or irreversible behavior. Afterwards, we focused on the modelir reversible traps. After an accurate identification of charging and discharging mechanisms, a SRH model led extract traps physical properties. Finally, we have investigated another phenomenon resulting in an uncontr flat band voltage with an electrical and optical technique based on InternaI Photo-Emission.GRENOBLE1-BU Sciences (384212103) / SudocSudocFranceF

Impact of High-Mobility Materials on the Performance of Near- and Sub-Threshold CMOS Logic Circuits

This paper studies the impact of high-mobility materials on the performance and energy efficiency of near- and sub- threshold CMOS logic circuits by means of analytical equations and experimental data on SiGe pMOSFETs. The introduction of high-mobility materials is shown to improve the energy- performance trade-off in near-threshold circuits more than in above-threshold circuits, since the benefits of higher mobility are degraded at higher longitudinal and transversal electric fields. On the other hand, results show that high-mobility materials do not exhibit any advantage in terms of the energy-performance trade-off in sub-threshold logic circuits. This is explained by the fact that the benefits brought by the larger mobility of SiGe or other alternative materials can be obtained by tuning the threshold voltage of conventional Si devices

III-V Devices for Advanced CMOS

peer reviewe