FPGA-based Accelerators for cryptography

Cryptography involves mathematical theory and encryption meth- ods. Cryptography algorithms are designed around computational hardness assumptions. This leads to heavy computational intensive algorithms. Sometimes a software approach could not be enough, but a hardware approach could be very complex. In this project, we present a halfway between software and hardware approach using an FPGA. The intended outcome of the project is the design and development of two hardware-based accelerators for cryptography that can be dynamically loaded into the FPGA. Mul- tiple approaches are presented during the project in order to design and test the accelerators

Amplifying On-Chip Memory Storage Capacity via Compression for Neural Network Workloads

Deep Neural Networks (DNNs) have been proven to be state-of-the-art for many applications. DNNs are an excellent target for hardware acceleration for several reasons: they are essentially a large collection of independent multiply-accumulate operations, they require large amounts of data to be transferred, and they are deployed in an ever increasing set of applications. Hence, hardware acceleration for DNNs has been a highly active area in research and development where new designs and techniques are proposed to achieve faster and more energy-efficient DNN execution on hardware. The need to investigate such hardware acceleration techniques requires tools that allow us to experiment with such methods and to estimate their potential performance and energy benets. Accordingly, this thesis targets two main contributions: 1) DNNsim, a DNN hardware accelerators simulator to evaluate new designs, and 2) Boveda, an on-chip memory compression technique designed for Deep Learning accelerator memory hierarchies.M.A.S