A software-programmable vision system-on-chip for high-speed image acquisition and processing

The IAP VSoC2M is a novel member of the Fraunhofer Vision System-on-Chip (VSoC) family for high-speed image acquisition and processing applications. It combines a multitude of innovative approaches such as analog convolution of image data during the readout process, fast column-parallel image analysis and feature extraction, column-specific storage of intermediate processing results in an analog cache with 32 entries each, column-parallel software-defined A/D-converters with 1...10 Bit resolution, an asynchronous readout path for compression of sparse data and an ASIP processor concept (application-specific instruction set) for software-defined control of all processes on the VSoC. The combination of all these features opens up a variety of new possibilities in embedded image processing that could not be implemented up to now. Possible applications range from a content-based automatic multi region of interest (ROI) image acquisition via optical measuring methods such as sheet of light (SoL) or optical coherence tomography (OCT) to the possibility of process control based on extracted image characteristics. On the basis of the VSoC, an OEM sensor module for integration into customer cameras and a complete industrial camera were developed with which specific image processing tasks can be realized

A Vision System-on-Chip with Multi-Stage Compressing Readout: Presentation held at 4th European Machine Vision Forum 2019, 4-6 September 2019, Campus LyonTech-la Doua, Villeurbanne (Lyon), France

In recent years, the research field of industrial image processing and machine vision has undergone rapid development. Optical resolution, frame rate and dynamic range dominated attention in this regard. The data processing in most cases is carried out in PC-based systems with or without GPU support, whereby a very effective implementation of even the most complex image processing or measurement solutions is possible using image processing libraries such as OpenCV, Halcon and others. However, this general approach reaches its limits in certain applications. Especially if the available bandwidths of interfaces along the image processing chain between sensor and result output are not sufficient or the latencies are too high to handle the envisaged tasks, appropriate measures have to be taken. Basically, there are only two possibilities. Either the amount of data and thus the optical, temporal or dynamic resolution of the image signal is reduced or the location of processing along the chain is shifted closer to the image acquisition. Depending on the data and its redundancy in the sense of the processing task, a considerable reduction can be achieved and the interfaces between the processing stages can be used much better. The reduction of the amount of image data even before the sensor chip output allows for massive reduction of the downstream camera-integrated data processing and thus the costs for the entire image processing system. By adapting the image acquisition, i.e. controlling the sensor matrix and A/D conversion of the pixel values to the observed physical process or optical set-up, additional power dissipation and thus processing efficiency can be improved. This work aims to supplement a software-programmable Vision System-on-Chip (VSoC) with multi-stage compressed readout and column-parallel image pre-processing, which can solve the exemplarily listed tasks in a particularly efficient way and at the same time can be used in a multitude of other applications due to its flexible architecture. (VSoC) with multi-stage compressed readout and column-parallel image pre-processing, which can solve the exemplarily listed tasks in a particularly efficient way and at the same time can be used in a multitude of other applications due to its flexible architecture