High-Level-Synthesis by Constraint Logic Programming

Integer programming has become popular to synthesis since it allows to compute optimal solutions by efficient formal methods. The drawback of this approach to synthesis is its resticted mathematical model. We adopted the basic idea of handling the synthesis problem as a constraint satisfaction problem and focus on solving it by constraint search. We use constraint logic programming, which is more flexible with repect to the representation of constrains

Exploiting Isomorphism for Speeding-Up Instance-Binding in an Integrated Scheduling, Allocation and Assignment Approach to Architectural Synthesis

Register-Transfer (RT-) level netlists are said to be isomorphic if they can be made identical by relabeling RT-components. RT-netlists can be generated by architectural synthesis. In order to consider just the essential design decisions, architectural synthesis should consider only a single representative of sets of isomorphic netlists. In this paper, we are using netlist isomorphism for the very rst time in architectural synthesis. Furthermore, we describe how an integer-programming (IP-) based synthesis technique can be extended to take advantage of netlist isomorphism

A Technique for Avoiding Isomorphic Netlists in Architectural Synthesis

Register-Transfer (RT-) level netlists are said to be isomorphic if they can be made identical by relabelling RT-components. RT-netlists can be generated by architectural synthesis. In order to consider just the essential design decisions, architectural synthesis should consider only a single representative of sets of isomorphic netlists. Nevertheless, many current synthesis algorithms do not take advantage of this potential reduction in search space. This is especially true for approaches which focus on optimizing the wiring between resource instances. In this paper, we are using netlist isomorphism for the very first time in architectural synthesis. Furthermore, we describe how an integer-programming (IP-) based synthesis technique can be extended to take advantage of netlist isomorphism. As a result, the running time required for synthesis is reduced. On leave from the University of Dortmund. Supported through NATO grant # CRG 950910. y Current affiliation: Universitat Dortmund,..

A Technique for Avoiding Isomorphic Netlists in Architectural Synthesis

Register-Transfer (RT-) level netlists are said to be isomorphic if they can be made identical by relabelling RT-components. RT-netlists can be generated byarchitectural synthesis. In order to consider just the essential design decisions, architectural synthesis should consider only a single representative of sets of isomorphic netlists. Nevertheless, many current synthesis algorithms do not take advantage of this potential reduction in search space. This is especially true for approaches which focus on optimizing the wiring between resource instances. In this paper, we are using netlist isomorphism for the very rst time in architectural synthesis. Furthermore, we describe how an integer-programming (IP-) based synthesis technique can be extended to take advantage of netlist isomorphism. As a result, the running time required for synthesis is reduced