Factor graph based detection approach for high-mobility OFDM systems with large FFT modes

In this article, a novel detector design is proposed for orthogonal frequency division multiplexing (OFDM) systems over frequency selective and time varying channels. Namely, we focus on systems with large OFDM symbol lengths where design and complexity constraints have to be taken into account and many of the existing ICI reduction techniques can not be applied. We propose a factor graph (FG) based approach for maximum a posteriori (MAP) symbol detection which exploits the frequency diversity introduced by the ICI in the OFDM symbol. The proposed algorithm provides high diversity orders allowing to outperform the free-ICI performance in high-mobility scenarios with an inherent parallel structure suitable for large OFDM block sizes. The performance of the mentioned near-optimal detection strategy is analyzed over a general bit-interleaved coded modulation (BICM) system applying low-density parity-check (LDPC) codes. The inclusion of pilot symbols is also considered in order to analyze how they assist the detection process

Design, simulation and implementation of a channel equalizer for DVB-T on-channel repeaters

This article describes the design and implementation of a channel equalizer for a terrestrial digital television (Digital Video Broadcasting-Terrestrial, DVB-T) on-channel repeater, namely gap-filler. Two are the benefits of including this equalizer in a repeater setup: on one hand, the transmitted signal requires a lower dynamic range and its degradation becomes smaller at the output amplifiers, thus allowing for a higher transmit power for the same modulation error rate (MER). On the other hand, it eases the equalization and decoding processes at the final receiver by improving its operation conditions. In this context, we present a novel low-cost equalizer architecture for mid-range and domestic gap-fillers. The design, implementation and validation methodology is also described, from the initial Matlab and Advanced Design System (ADS) simulations to the final hardware implementation, based on a field programmable gate array (FPGA) device and a Blackfin digital signal processor (DSP). The obtained practical results assess the performance gains predicted by simulation, hence proving the validity and efficacy of the designed equalizer to reduce the cost of the amplifiers and to obtain a better signal quality at the final user's receiver.Peer reviewe