Speed performances of thin-film lateral SOI PIN photodiodes up to tens of GHz

The present paper investigates performances of SOI PIN detectors in function of their intrinsic length, L/sub i/. Our original model, fully validated by Atlas 2D numerical simulations and measurements, allows to predict and optimize their speed performances for the target applications.Anglai

Low-voltage low-power high-temperature SOI CMOS rectifiers

In this paper we introduce the use of low-drop voltage low-leakage CMOS SOI diodes to improve the power efficiency of AC-DC power converter for low-voltage and high-temperature applications

Novel capacitor-less 1T-DRAM using MSD effect

In this paper, we propose a different single-transistor capacitor-less DRAM which is operated at low drain voltage and enables low-power applications. The basic mechanism is the meta-stable dip (MSD) effect recently discovered (Bawedin et al., 2004, 2005). MSD gives rise to a hysteresis in ID(VG) curves and a dip in transconductance gm. We demonstrate by systematic measurements and simulations that MSDRAMs with long retention time can be achieved

First Report on Self-Switching-Diodes in SOI

The work on SOI shows that SSDs can be compatible with advanced CMOS on SOI technologies, which greatly enhances the possibilities to practically use SSDs. One of the most significant advantages of SSDs is the remarkably simple process requiring only to create trenches in a semiconductor film. By combining a few SSDs, simple logic gates can be fabricated also in one lithography step (Song, 2003). The SSDs can also be used as memory cells working at room temperature as demonstrated in ref. 6. Furthermore, one can form a lateral gate on one side of the channel thus making a self-switching transistor (SST) opening more possibilities for applications. These various devices are under fabrication on SOI and characterisation in our group. We believe that that SSDs on SOI may provide remarkable simplicity and flexibility in circuit design and fabricatio

Performance of SOI devices transferred onto passivated HR SOI substrates using a layer transfer technique

High resistivity (HR) silicon wafers are promising candidates for RF applications due, mainly, to their low cost, CMOS compatibility and substantial substrate loss reduction (Eggert et al., 1997). However, oxidized HR silicon (such as HR SOI material) is known to suffer from parasitic surface conduction (PSC) below the oxide (Gamble et al., 1999) which can reduce the effective resistivity ( rho /sub eff/) of the wafers by more than one order of magnitude (Lederer and Raskin, 2003). This issue can be overcome by introducing a trap-rich passivation layer between the oxide and the Si substrate, such as polysilicon (Gamble et al., 1999). In this paper we demonstrate for the first time that: (1) polySi substrate passivation can be efficiently realized on an industrial SOI technology using a post-process circuit transfer technique and that: (2) this technique preserves the performance of active devices.Anglai

DTMOS low noise amplifier design in partially depleted SOI CMOS technology

This paper reviews and analyzes a low-noise amplifier (LNA) for low-power applications using a cascode inductive source degeneration topology, with a dynamic threshold MOSFET (DTMOS) transistor in 130 nm CMOS SOI technology. Thanks to the introduction of dynamic threshold-voltage MOSFET (DTMOS), the measurement of the LNA shows 13 dB gain and -30 dB reflection input, while dissipating 6 mW under 1.2 V supply.Anglai