Synthesis of Pipelined DSP Accelerators with Dynamic Scheduling

To construct complete systems on silicon, application specific DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology is presented to synthesize high throughput DSP functions into accelerator processors containing a datapath of highly pipelined, bit-parallel hardware units. Emphasis will be put on the definition of a controller architecture that allows efficient run-time schedules of these DSP algorithms on such highly pipelined data paths. The methodology will be illustrated by means of an image encoding filter bank. I. Introduction C OMPLEX digital systems such as the videophone terminal of figure 1 typically consist out of a heterogeneous mix of hardware blocks [1]: processor cores, general purpose macro blocks, and dedicated accelerator processors. These accelerator blocks are required to execute high performant DSP functions such as motion estimation and DCT/IDCT functions. In this paper we will concentrate on the ge..

Fast software implementation of the MPEG-4 reversible integer wavelet transform on Pentium MMX, Sharc ADSP and Trimedia TM1000

info:eu-repo/semantics/publishe

Data compression method and apparatus

info:eu-repo/semantics/publishe

Hardware/software partitioning of embedded system in ocapi-xl

The implementation of embedded networked appliances requires a mix of processor cores and HW accelerators on a single chip. When designing such complex and heterogeneous SoCs, the HW / SW partitioning decision needs to be made prior to refining the system description. With OCAPI-xl, we developed a methodology in which the partitioning decision can be made anywhere in the design flow, even just prior to doing code-generation for both HW and SW. This is made possible thanks to a refinable, implementable, architecture independent system description. The OCAPI-xl model was used to develop a stand alone, networked camera, with onboard GIF engine and network layer. 1

Methodological reduction of Memory Requirements for a VLSI Spaceborne Wavelet Compression Engine

info:eu-repo/semantics/publishe

Space-filling curves in Advanced Image Compression applications

info:eu-repo/semantics/publishe

Optimal Memory Organization for scalable texture codecs in MPEG-4

info:eu-repo/semantics/publishe

Smile - a Scalable Microcontroller Library Element

A parameterised microcontroller for use in compiled single-chip systems is described. Key processor parameters may be varied over a wide range (minimum data bus width is 4 bits) in order to optimise chip area and performance for a given application. The instruction set is uniform and compact, does not vary when the microcontroller design is scaled, and produces dense code. A working prototype has been produced in Mietec 2.4mu CMOS using the Cathedral silicon compiler, and a variety of 1.2mu and 0.7mu layouts generated from parameterised netlists in the Hilarics and VHDL languages, using both the Cathedral and Synopsys compilers. Code density and layout results are given