A Survey on the Modeling of Magnetic Tunnel Junctions for Circuit Simulation

Spin-transfer torque-based magnetoresistive random access memory (STT-MRAM) is a promising candidate for universal memory that may replace traditional memory forms. It is expected to provide high-speed operation, scalability, low-power dissipation, and high endurance. MRAM switching technology has evolved from the field-induced magnetic switching (FIMS) technique to the spin-transfer torque (STT) switching technique. Additionally, material technology that induces perpendicular magnetic anisotropy (PMA) facilitates low-power operation through the reduction of the switching current density. In this paper, the modeling of magnetic tunnel junctions (MTJs) is reviewed. Modeling methods and models of MTJ characteristics are classified into two groups, macromodels and behavioral models, and the most important characteristics of MTJs, the voltage-dependent MTJ resistance and the switching behavior, are compared. To represent the voltage dependency of MTJ resistance, some models are based on physical mechanisms, such as Landau-Lifshitz-Gilbert (LLG) equation or voltage-dependent conductance. Some behavioral models are constructed by adding fitting parameters or introducing new physical parameters to represent the complex switching behavior of an MTJ over a wide range of input current conditions. Other models that are not based on physical mechanisms are implemented by simply fitting to experimental data

A Survey on the Modeling of Magnetic Tunnel Junctions for Circuit Simulation

Spin-transfer torque-based magnetoresistive random access memory (STT-MRAM) is a promising candidate for universal memory that may replace traditional memory forms. It is expected to provide high-speed operation, scalability, low-power dissipation, and high endurance. MRAM switching technology has evolved from the field-induced magnetic switching (FIMS) technique to the spin-transfer torque (STT) switching technique. Additionally, material technology that induces perpendicular magnetic anisotropy (PMA) facilitates low-power operation through the reduction of the switching current density. In this paper, the modeling of magnetic tunnel junctions (MTJs) is reviewed. Modeling methods and models of MTJ characteristics are classified into two groups, macromodels and behavioral models, and the most important characteristics of MTJs, the voltage-dependent MTJ resistance and the switching behavior, are compared. To represent the voltage dependency of MTJ resistance, some models are based on physical mechanisms, such as Landau-Lifshitz-Gilbert (LLG) equation or voltage-dependent conductance. Some behavioral models are constructed by adding fitting parameters or introducing new physical parameters to represent the complex switching behavior of an MTJ over a wide range of input current conditions. Other models that are not based on physical mechanisms are implemented by simply fitting to experimental data

New Simulation Method for Dependency of Device Degradation on Bending Direction and Channel Length

The dependency of device degradation on bending direction and channel length is analyzed in terms of bandgap states in amorphous indium-gallium-zinc-oxide (a-IGZO) films. The strain distribution in an a-IGZO film under perpendicular and parallel bending of a device with various channel lengths is investigated by conducting a three-dimensional mechanical simulation. Based on the obtained strain distribution, new device simulation structures are suggested in which the active layer is defined as consisting of multiple regions. The different arrangements of a highly strained region and density of states is proportional to the strain account for the measurement tendency. The analysis performed using the proposed structures reveals the causes underlying the effects of different bending directions and channel lengths, which cannot be explained using the existing simulation methods in which the active layer is defined as a single region

Circuit Optimization Method to Reduce Disturbances in Poly-Si 1T-DRAM

A capacitorless one-transistor dynamic random-access memory device (1T-DRAM) is proposed to resolve the scaling problem in conventional one-transistor one-capacitor random-access memory (1T-1C-DRAM). Most studies on 1T-DRAM focus on device-level operation to replace 1T-1C-DRAM. To utilize 1T-DRAM as a memory device, we must understand its circuit-level operation, in addition to its device-level operation. Therefore, we studied the memory performance depending on device location in an array circuit and the circuit configuration by using the 1T-DRAM structure reported in the literature. The simulation results show various disturbances and their effects on memory performance. These disturbances occurred because the voltages applied to each device during circuit operation are different. We analyzed the voltage that should be applied to each voltage line in the circuit to minimize device disturbance and determine the optimized bias condition and circuit structure to achieve a large sensing margin and realize operation as a memory device. The results indicate that the memory performance improves when the circuit has a source line and the bias conditions of the devices differ depending on the write data at the selected device cell. Therefore, the sensing margin of the 1T-DRAM used herein can expectedly be improved by applying the proposed source line (SL) structure

Optimization Considerations for Short Channel Poly-Si 1T-DRAM

Capacitorless one-transistor dynamic random-access memory cells that use a polysilicon body (poly-Si 1T-DRAM) have been studied to overcome the scaling issues of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Generally, when the gate length of a silicon-on-insulator (SOI) structure metal-oxide-silicon field-effect transistor (MOSFET) is reduced, its body thickness is reduced in order to suppress the short-channel effects (SCEs). TCAD device simulations were used to investigate the transient performance differences between thin and thick-body poly-Si DRAMs to determine whether reduced body thickness is also appropriate for those devices. Analysis of the simulation results revealed that operating bias conditions are as important as body thickness in 1T-DRAM operation. Since a thick-body device has more trapped hole charge in its grain boundary (GB) than a thin-body device in both the “0” and “1” states, the transient performance of a thick-body device is better than a thin-body device regardless of the Write”1” drain voltage. We also determined that the SCEs in the memory cells can be improved by lowering the Write”1” drain voltage. We conclude that an optimization method for the body thickness and voltage conditions that considers both the cell’s SCEs and its transient performance is necessary for its development and application

A Unified Current-Voltage Model for Metal Oxide-Based Resistive Random-Access Memory

Resistive random-access memory (RRAM) is essential for developing neuromorphic devices, and it is still a competitive candidate for future memory devices. In this paper, a unified model is proposed to describe the entire electrical characteristics of RRAM devices, which exhibit two different resistive switching phenomena. To enhance the performance of the model by reflecting the physical properties such as the length index of the undoped area during the switching operation, the Voltage ThrEshold Adaptive Memristor (VTEAM) model and the tungsten-based model are combined to represent two different resistive switching phenomena. The accuracy of the I–V relationship curve tails of the device is improved significantly by adjusting the ranges of unified internal state variables. Furthermore, the unified model describes a variety of electrical characteristics and yields continuous results by using the device’s current-voltage relationship without dividing its fitting conditions. The unified model describes the optimized electrical characteristics that reflect the electrical behavior of the device