Performance Implications of Synchronization Support for Parallel FORTRAN Programs

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryJoint Services Electronics Program / N00014-90-J-1270National Science Foundation / MIP-8809478National Aeronautics and Space Administration / NASA NAG 1-613NCRAMD 29K Advanced Processor Development Divisio

Single-Pass Memory System Evaluation for Multiprogramming Workloads

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryNational Science Foundation (NSF) / MIP-8809478NCRNational Aeronautics and Space Administration (NASA) / NASA NAG 1-613Office of Naval Research / N00014-88-K-065

Combining Sampling with Single-Pass Techniques for Efficient Cache Simulation

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryNCRNational Science Foundation / MIP-8809478Hewlett-Packar

Profile-Guided Automatic Inline Expansion for C Programs

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryNational Science Foundation / MIP-8809478NCRAMD 29K Advanced Processor Development DivisionNational Aeronautics and Space Administration / NASA NAG 1-61

The Susceptibility of Programs to Context Switching

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryNational Science Foundation / MIP-8809478NCR Corp.AMD Corp. 29K Advanced Processor Development DivisionNational Aeronautics and Space Administration / NASA NAG 1-613Office of Naval Research / N00014-88-K-0656Hewlett-Packard Co

Efficient Instruction Sequencing with Inline Target Insertion

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryNational Science Foundation / MIP-8809478NCRNational Aeronautics and Space Administration / NASA NAG 1-613Office of Naval Research / N00014-88-K-065

Compiler-Assisted Signature Monitoring

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryJoint Services Electronics Program / N00014-84-C-0149Office of Naval Research / N00014-88-K-0656National Science Foundation / MIP-8809478NCRNational Aeronautics and Space Administration / NASA NAG 1-61

Compiler-assisted multiple instruction rollback recovery using a read buffer

Multiple instruction rollback (MIR) is a technique that has been implemented in mainframe computers to provide rapid recovery from transient processor failures. Hardware-based MIR designs eliminate rollback data hazards by providing data redundancy implemented in hardware. Compiler-based MIR designs have also been developed which remove rollback data hazards directly with data-flow transformations. This paper describes compiler-assisted techniques to achieve multiple instruction rollback recovery. We observe that some data hazards resulting from instruction rollback can be resolved efficiently by providing an operand read buffer while others are resolved more efficiently with compiler transformations. The compiler-assisted scheme presented consists of hardware that is less complex than shadow files, history files, history buffers, or delayed write buffers, while experimental evaluation indicates performance improvement over compiler-based schemes

The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryNational Science Foundation / MIP-8809478NCRAMD 29K Advanced Processor Development DivisionNational Aeronautics and Space Administration / NASA NAG 1-613U.S. Department of Energy / DOE DE-FGO2-85ER25001IBM Corporatio