Resting-State Brain Variability in Youth With Attention-Deficit/Hyperactivity Disorder

In this study, we sought to determine the nature of the abnormality in resting-state default mode network (DMN) activation and explore its correlation with functional connectivity in attention-deficit/hyperactivity disorder (ADHD). We obtained resting-state functional magnetic resonance images of youth with ADHD and typically developing counterparts from the publicly available ADHD-200 database. We used data from Peking University (232 scans) and New York University (172 scans); the scan repetition time was 2 s for both data collection sites. We applied generalized estimating equations to estimate the variability of the averaged blood-oxygen-level-dependent (BOLD) time series extracted from the DMN at rest. We performed network-based statistics to determine the association between the observed differences in BOLD signal variability and altered functional connectivity. We analyzed data from 105 youth with ADHD (age: mean 12.17, standard deviation 2.31, median 12.25; 15.2% female, 84.8% male) and 140 typically developing youth (age: mean 11.99, standard deviation 2.28, median 11.85; 47.1% female, 52.9% male), who aged 7-17 years. The imaging data were cross-sectionally collected for each participant at one time point. We observed a greater number of significant BOLD signal changes and higher-order polynomial significant associations in youth with ADHD. Moreover, there were significant between-group differences in BOLD signal change after the first 140 s, which coincided with decreased resting-state functional connectivity within the DMN in youth with ADHD. Increased variability of neural signaling was intermittently observed in the brains of youth with ADHD at rest, thereby indicating their default mode state was more unstable than that of typically developing youth.N

High-Throughput and Low-Latency Digital Baseband Architecture for Energy-Efficient Wireless VR Systems

This paper presents a novel baseband architecture that supports high-speed wireless VR solutions using 60 GHz RF circuits. Based on the experimental observations by our previous 60 GHz transceiver circuits, the efficient baseband architecture is proposed to enhance the quality of transmission. To achieve a zero-latency transmission, we define an (106,920, 95,040) interleaved-BCH error-correction code (ECC), which removes iterative processing steps in the previous LDPC ECC standardized for the near-field wireless communication. Introducing the block-level interleaving, the proposed baseband processing successfully scatters the existing burst errors to the small-sized component codes, and recovers up to 1080 consecutive bit errors in a data frame of 106,920 bits. To support the high-speed wireless VR system, we also design the massive-parallel BCH encoder and decoder, which is tightly connected to the block-level interleaver and de-interleaver. Including the high-speed analog interfaces for the external devices, the proposed baseband architecture is designed in 65 nm CMOS, supporting a data rate of up to 12.8 Gbps. Experimental results show that the proposed wireless VR solution can transfer up to 4 K high-resolution video streams without using time-consuming compression and decompression, successfully achieving a transfer latency of 1 ms

Energy-Efficient Symmetric BC-BCH Decoder Architecture for Mobile Storages

Recently, symmetric block-wise concatenated-BCH (SBC-BCH) codes are proposed as strong error-correcting codes (ECCs) based on hard-decision channel outputs, which is especially suited for storages using NAND flash memories. Targeting energy-efficient NAND flash memory applications, this paper presents an energy-optimized decoder architecture which includes an iterative decoder for a SBC-BCH code as a main decoder and a low-complexity auxiliary decoder for a block-wise single parity-check (BSPC) code. The auxiliary decoder is opportunistically in action to break the dominant error bound associated with the SBC-BCH code, which allows one to lower the uncorrectable bit-error-rate (UBER) to 10(-15) in an energy efficient way. This work presents several design-level optimizations for further enhancing the energy-efficiency of the iterative SBC-BCH decoder. More precisely, the new initialization scheme is proposed for ensuring the energy-efficient seamless decoding scenario. The syndrome tracking is applied to eliminate the previous syndrome calculation and the reordered Chien search further enhances the energy-efficiency as well as the decoding throughput. Targeting a 0.9-rate 4KB SBC-BCH code for commercialized storages using NAND flash memories, a prototype decoder consisting of both the iterative main and auxiliary decoders is designed in a 65-nm CMOS process. By applying the proposed optimizations, the prototype decoder achieves an energy-efficiency of 3.43 pJ/b while providing a decoding throughput of 13.2 Gb/s, which is superior to the previous state-of-the-art decoders for mobile storages.11Nsciescopu