13 research outputs found
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Performance measurements of hybrid PIN diode arrays
We report the successful development of hybrid PIN diode arrays and a series of room-temperature measurements in a high-energy pion beam at FNAL. A PMOS VLSI 256 {times} 256 readout array having 30 {mu}m square pixels was indium-bump bonded to a mating PIN diode detector array. Preliminary measurements on the resulting hybrid show excellent signal-to-noise at room temperature. 3 refs., 5 figs
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Development of a customized SSC pixel detector readout for vertex tracking
We describe the readout architecture and progress to date in the development of hybrid PIN diode arrays for use as vertex detectors in the SSC environment. The architecture supports a self-timed mechanism for time stamping hit pixels, storing their xy coordinates and later selectively reading out only those pixels containing interesting data along with their coordinates. The peripheral logic resolves ambiguous pixel ghost locations and controls pixel neighbor readout to achieve high spatial resolution. A test lot containing 64 {times} 32 pixel arrays has been processed and is currently being tested. Each pixel contains 23 transistors and six capacitors consuming an area of 50 {mu}m by 150 {mu}m and dissipating about 20{mu}W of power. 6 refs., 2 figs
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Development of pixel detectors for SSC vertex tracking
A description of hybrid PIN diode arrays and a readout architecture for their use as a vertex detector in the SSC environment is presented. Test results obtained with arrays having 256 {times} 256 pixels, each 30 {mu}m square, are also presented. The development of a custom readout for the SSC will be discussed, which supports a mechanism for time stamping hit pixels, storing their xy coordinates, and storing the analog information within the pixel. The peripheral logic located on the array, permits the selection of those pixels containing interesting data and their coordinates to be selectively read out. This same logic also resolves ambiguous pixel ghost locations and controls the pixel neighbor read out necessary to achieve high spatial resolution. The thermal design of the vertex tracker and the proposed signal processing architecture will also be discussed. 5 refs., 13 figs., 3 tabs