In Vitro Fertilized Embryos do not Secrete Detectable HLA-G on Day Two

ABSTRACT Background: Pregnancy is a successful transplantation. The factors evading rejection of the fetus are poorly understood. Recently an interest has grown, in HLA-G molecules as one of these factors. Since these antigens are mainly expressed on the surface of cytotrophoblasts that are in direct contact with maternal tissues, it has been suggested that these molecules may have a role in induction of immune tolerance in mothers. Objective: to find the association of soluble HLA-G (sHLA-G) and the success of pregnancy with intracytoplasmic sperm injection (ICSI) procedure. Methods: In this study, the supernatant of 287 individually cultured embryos corresponding to 96 women under ICSI procedure were assayed for soluble HLA-G1 and G5 by a sandwich ELISA. Results: Clinical pregnancy successfully occurred in 30 of candidates. No differences in clinical parameters (age, infertility duration, stimulation regimen) were observed between pregnant and nonpregnant women under ICSI procedure. None of the embryo supernatants in either group showed any detectable sHLA-G molecules. Conclusion: Our results showed that detectable level of sHLA-G is not produced by day 2 embryos and such a measurement may not provide reliable information for embryo selection and estimation of pregnancy success

An Offset-free High linear Low Power High Speed Four-Quadrant MTL Multiplier

In this paper a new CMOS current-mode four-quadrant analog multiplier circuit is proposed. The major advantages of this design are high linearity, high speed and low power consumption. Removing dc offset is the most important improvement in this topology. The circuit is designed with 1.8V supply voltage and is simulated using HSPICE simulator by level 49 parameters in 0.18µm standard CMOS TSMC technology. The aspect ratios of the MOSFETs are optimized using Evolutionary algorithm by MATLAB. The simulation results of this analog multiplier demonstrate a maximum linearity error of 2.6%, a THD of 1.77%, maximum power consumption of 157 µW, -3dB bandwidth of 241MHz and almost free from dc offset