Write-Optimized Dynamic Hashing for Persistent Memory

Low latency storage media such as byte-addressable persistent memory (PM) requires rethinking of various data structures in terms of optimization. One of the main challenges in implementing hash-based indexing structures on PM is how to achieve efficiency by making effective use of cachelines while guaranteeing failure-atomicity for dynamic hash expansion and shrinkage. In this paper, we present Cacheline-Conscious Extendible Hashing (CCEH) that reduces the overhead of dynamic memory block management while guaranteeing constant hash table lookup time. CCEH guarantees failure-atomicity without making use of explicit logging. Our experiments show that CCEH effectively adapts its size as the demand increases under the finegrained ailure-atomicity constraint and its maximum query latency is an order of magnitude lower compared to the stateof-the-art ashing techniques

Pivotal B plus tree for Byte-Addressable Persistent Memory

Over the past few years, various indexes have been redesigned for byte-addressable persistent memory. In this work, we design and implement PB+tree (Pivotal B+tree) that resolves the limitations of state-of-the-art fully persistent B+trees. First, PB+tree reduces the number of expensive shift operations by up to half by managing two sub-arrays separated by a pivot key. Second, PB+tree reads cachelines in ascending order, which makes PB+tree benefit from hardware prefetchers and run faster than state-of-the-art persistent B+trees that access cachelines in non-contiguous or descending order. Third, PB+tree employs an optimistic lock-free search algorithm to avoid repeatedly visiting the same tree node. Although the optimistic lock-free search algorithm involves a risk of visiting incorrect child nodes, PB+tree guarantees correct search results using the lazy correction algorithm using doubly linked sibling pointers. Our performance study shows that PB+tree outperforms the state-of-the-art fully persistent indexes by a large margin. A search algorithm without optimistic locking risks visiting the wrong child node, but PB+tree uses a lazy correction algorithm with doubly linked sibling pointers to ensure correct search results. Our performance studies show that PB+trees outperform state-of-the-art fully persistent indexes

A beta-induced mitochondrial dysfunction in neural progenitors controls KDM5A to influence neuronal differentiation

© 2022, The Author(s).Mitochondria in neural progenitors play a crucial role in adult hippocampal neurogenesis by being involved in fate decisions for differentiation. However, the molecular mechanisms by which mitochondria are related to the genetic regulation of neuronal differentiation in neural progenitors are poorly understood. Here, we show that mitochondrial dysfunction induced by amyloid-beta (Aβ) in neural progenitors inhibits neuronal differentiation but has no effect on the neural progenitor stage. In line with the phenotypes shown in Alzheimer’s disease (AD) model mice, Aβ-induced mitochondrial damage in neural progenitors results in deficits in adult hippocampal neurogenesis and cognitive function. Based on hippocampal proteome changes after mitochondrial damage in neural progenitors identified through proteomic analysis, we found that lysine demethylase 5A (KDM5A) in neural progenitors epigenetically suppresses differentiation in response to mitochondrial damage. Mitochondrial damage characteristically causes KDM5A degradation in neural progenitors. Since KDM5A also binds to and activates neuronal genes involved in the early stage of differentiation, functional inhibition of KDM5A consequently inhibits adult hippocampal neurogenesis. We suggest that mitochondria in neural progenitors serve as the checkpoint for neuronal differentiation via KDM5A. Our findings not only reveal a cell-type-specific role of mitochondria but also suggest a new role of KDM5A in neural progenitors as a mediator of retrograde signaling from mitochondria to the nucleus, reflecting the mitochondrial status.N

B-3-Tree: Byte-Addressable Binary B-Tree for Persistent Memory

In this work, we propose B-3-tree, a hybrid index for persistent memory that leverages the byte-addressability of the in-memory index and the page locality of B-trees. As in the byte-addressable in-memory index, B-3-tree is updated by 8-byte store instructions. Also, as in disk-based index, B-3-tree is failure-atomic since it makes every 8-byte store instruction transform a consistent index into another consistent index without the help of expensive logging. Since expensive logging becomes unnecessary, the number of cacheline flush instructions required for B-3-tree is significantly reduced. Our performance study shows that B-3-tree outperforms other state-of-the-art persistent indexes in terms of insert and delete performance. While B-3-tree shows slightly worse performance for point query performance, the range query performance of B-3-tree is 2x faster than FAST and FAIR B-tree because the leaf page size of B-3-tree can be set to 8x larger than that of FAST and FAIR B-tree without degrading insertion performance. We also show that read transactions can access B-3- tree without acquiring a shared lock because B-3-tree remains always consistent while a sequence of 8-byte write operations are making changes to it. As a result, B-3-tree provides high concurrency level comparable to FAST and FAIR B-tree