2 research outputs found
Analog Feedback-Controlled Memristor programming Circuit for analog Content Addressable Memory
Recent breakthroughs in associative memories suggest that silicon memories
are coming closer to human memories, especially for memristive Content
Addressable Memories (CAMs) which are capable to read and write in analog
values. However, the Program-Verify algorithm, the state-of-the-art memristor
programming algorithm, requires frequent switching between verifying and
programming memristor conductance, which brings many defects such as high
dynamic power and long programming time. Here, we propose an analog
feedback-controlled memristor programming circuit that makes use of a novel
look-up table-based (LUT-based) programming algorithm. With the proposed
algorithm, the programming and the verification of a memristor can be performed
in a single-direction sequential process. Besides, we also integrated a single
proposed programming circuit with eight analog CAM (aCAM) cells to build an
aCAM array. We present SPICE simulations on TSMC 28nm process. The theoretical
analysis shows that 1. A memristor conductance within an aCAM cell can be
converted to an output boundary voltage in aCAM searching operations and 2. An
output boundary voltage in aCAM searching operations can be converted to a
programming data line voltage in aCAM programming operations. The simulation
results of the proposed programming circuit prove the theoretical analysis and
thus verify the feasibility to program memristors without frequently switching
between verifying and programming the conductance. Besides, the simulation
results of the proposed aCAM array show that the proposed programming circuit
can be integrated into a large array architecture
Memristor-based hardware and algorithms for higher-order Hopfield optimization solver outperforming quadratic Ising machines
Ising solvers offer a promising physics-based approach to tackle the
challenging class of combinatorial optimization problems. However, typical
solvers operate in a quadratic energy space, having only pair-wise coupling
elements which already dominate area and energy. We show that such
quadratization can cause severe problems: increased dimensionality, a rugged
search landscape, and misalignment with the original objective function. Here,
we design and quantify a higher-order Hopfield optimization solver, with 28nm
CMOS technology and memristive couplings for lower area and energy
computations. We combine algorithmic and circuit analysis to show quantitative
advantages over quadratic Ising Machines (IM)s, yielding 48x and 72x reduction
in time-to-solution (TTS) and energy-to-solution (ETS) respectively for Boolean
satisfiability problems of 150 variables, with favorable scaling