516 research outputs found

    Graphical modelling language for spycifying concurrency based on CSP

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    Introduced in this (shortened) paper is a graphical modelling language for specifying concurrency in software designs. The language notations are derived from CSP and the resulting designs form CSP diagrams. The notations reflect both data-flow and control-flow aspects of concurrent software architectures. These designs can automatically be described by CSP algebraic expressions that can be used for formal analysis. The designer does not have to be aware of the underlying mathematics. The techniques and rules presented provide guidance to the development of concurrent software architectures. One can detect and reason about compositional conflicts (errors in design), potential deadlocks (errors at run-time), and priority inversion problems (performance burden) at a high level of abstraction. The CSP diagram collaborates with objectoriented modelling languages and structured methods

    Managing complexity of control software through concurrency

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    In this thesis, we are concerned with the development of concurrent software for embedded systems. The emphasis is on the development of control software. Embedded systems are concurrent systems whereby hardware and software communicate with the concurrent world. Concurrency is essential, which cannot be ignored. It requires a proper handling to avoid pathological problems (e.g. deadlock and livelock) and performance penalties (e.g. starvation and priority conflicts). Multithreading, as such, leads to sources of complexity in concurrent software. This complexity is considered frightening, because it complicates the software designs and the resulting code. Moreover, this paradigm complicates the understanding of the behaviour of concurrent software. A paradigm with a precise understanding of concurrency is essential. In this thesis, a methodology is proposed that comprises a paradigm of fundamental aspects of concurrency

    Sampling and Timing: A Task for the Environmetal Process

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    Sampling and timing is considered a responsibility of the environment of controller software. In this paper we will illustrate a concept whereby an environmental process and multi-way events play an important role in applying timing for untimed CSP software architectures. We use this timing concept for building our control applications based on CSP concepts and with our CSP for C++ (CTC++) library. We present a concept of sampling of control applications that is orthogonal to the application. This implies global timing on the basis of timed events. We also support traditional local timing on the based of timed processes

    Building Blocks for Control System Software

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    Software implementation of control laws for industrial systems seem straightforward, but is not. The computer code stemming from the control laws is mostly not more than 10 to 30% of the total. A building-block approach for embedded control system development is advocated to enable a fast and efficient software design process.\ud We have developed the CTJ library, Communicating Threads for JavaÂż,\ud resulting in fundamental elements for creating building blocks to implement communication using channels. Due to the simulate-ability, our building block method is suitable for a concurrent engineering design approach. Furthermore, via a stepwise refinement process, using verification by simulation, the implementation trajectory can be done efficiently

    A distributed Real-Time Java system based on CSP

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    CSP is a fundamental concept for developing software for distributed real time systems. The CSP paradigm constitutes a natural addition to object orientation and offers higher order multithreading constructs. The CSP channel concept that has been implemented in Java deals with single- and multi-processor environments and also takes care of the real time priority scheduling requirements. For this, the notion of priority and scheduling has been carefully examined and as a result it was reasoned that priority scheduling should be attached to the communicating channels rather than to the processes. In association with channels, a priority based parallel construct is developed for composing processes: hiding threads and priority indexing from the user. This approach simplifies the use of priorities for the object oriented paradigm. Moreover, in the proposed system, the notion of scheduling is no longer connected to the operating system but has become part of the application instead

    Safe and Verifiable Design of Concurrent Java Programs

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    The design of concurrent programs has a reputation for being difficult, and thus potentially dangerous in safetycritical real-time and embedded systems. The recent appearance of Java, whilst cleaning up many insecure aspects of OO programming endemic in C++, suffers from a deceptively simple threads model that is an insecure variant of ideas that are over 25 years old [1]. Consequently, we cannot directly exploit a range of new CASE tools -- based upon modern developments in parallel computing theory -- that can verify and check the design of concurrent systems for a variety of dangers\ud such as deadlock and livelock that otherwise plague us during testing and maintenance and, more seriously, cause catastrophic failure in service. \ud Our approach uses recently developed Java class\ud libraries based on Hoare's Communicating Sequential Processes (CSP); the use of CSP greatly simplifies the design of concurrent systems and, in many cases, a parallel approach often significantly simplifies systems originally approached sequentially. New CSP CASE tools permit designs to be verified against formal specifications\ud and checked for deadlock and livelock. Below we introduce CSP and its implementation in Java and develop a small concurrent application. The formal CSP description of the application is provided, as well as that of an equivalent sequential version. FDR is used to verify the correctness of both implementations, their\ud equivalence, and their freedom from deadlock and livelock

    Photoluminescence and attenuation of spray-pyrolysis-deposited erbium-doped Y2O3 planar optical waveguides

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    Erbium-doped Y20 3 planar optical waveguides have been fabricated by spray-pyrolysis deposition. The attenuation spectrum of the waveguide shows peaks that are due to absorption of the erbium ions. The as-deposited layers also show photoluminescence sharply peaking at 1540 nm with additional Stark splitting. The thin layers of Er 3:Y 203 obtained are promising for the realization of integrated-optic amplifiers and lasers

    Embedded Software Design for Mechatronic Systems

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    This research project is motivated by the fact that nowadays it is impossible to separate control engineering from software engineering. Besides that both of them can be found in definitions of mechatronics, this project deals with exploitation and improvement of their strong natural interdependency. In all modern reactive systems, what all mechatronics systems are, one will always find one or more embedded computers. The functionality of these computers, and in turn controlled systems, is powered by embedded software [1]

    Multimode waveguides of Photodefinable epoxy for optical backplane applications

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    We developed photodefined, multimode-fiber compatible waveguides based on epoxies. These waveguides will be embedded in backplane PCB’s for optical interconnect applications using 850 nm VCSELs as light sources. Apart from very low loss, the material selection took into account, PCB compatibility and low yellowing due to high temperature processing (for PCB lamination and soldering). The waveguides showed losses < 0.06 dB/cm at 832 nm and 633 nm. Their loss increase after aging (1 hr at 185 °C) was limited to 0.04 dB/cm at 850 nm. Waveguides realized on FR-4 (epoxyfiberglass)PCB material are demonstrated
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