An 11 GHz-Bandwidth Variable Gain Ka-Band Power Amplifier for 5G Applications

A Ka-band,32-43 GHz,differential power amplifier (PA) for millimeter wave applications is presented. The PA is a three stage design with a nominal gain of 36 dB. A device periphery ratio of 1:2:4 is adopted for pre-driver,driver and final stage,respectively. To enable use of 2.7 V supply,a cascode topology was employed in all three stages. The input is 80 ω differential and the output load is 50 ω single ended. The PA has a variable gain of 36 ± 11 dB for use as variable gain amplifier. A saturation power of 17.8 dBm was measured at 35 GHz with a small signal gain of 34.5 dB,including output losses of 2-2.5 dB over band. The design is based on magnetically coupled parallel resonators to obtain the required bandwidth. A SiGe HBT BiCMOS process with fMAX = 330 GHz was used for fabrication. The PA is part of a front-end design,and its output thus faces an antenna interface with integrated LNA and TX/RX switches,and the input is connected to an on-chip variable gain amplifier

Broadband LDMOS 40 W and 55 W integrated power amplifiers

The performance of broadband microwave 40 W and 55 W LDMOS integrated power amplifiers is reported. A 30 V LDMOS process with 500 nm gate length was used for the design. Single and dual die packages were evaluated. A dual die package provides flexibility in output power and efficiency depending on combiner topology at the input and output of the circuit. Different saturated power and efficiency are obtained for different classes, Class A, AB and B operation and for different combiners, Wilkinson, quadrature or balun. Moreover, dual die in Doherty configuration provides a compact solution for better back-off efficiency in a symmetrical / asymmetrical topology. The 40 W design demonstrates 24 %, 1 dB fractional bandwidth around 2.1 GHz, and power added efficiency of 48 % at P-1 dB of 50 W. It showed excellent back-off linearity and best in class memory effect over frequency and temperature. The 55 W design has 28 %, 1 dB fractional bandwidth around 2.2 GHz, and power added efficiency of 49 % at P-1 dB equal to 63 W

An LO Frequency Tripler with Phase Shifter and Detector in 28nm FD-SOI CMOS for 28-GHz Transceivers

This paper presents an LO frequency multiplier and phase shifter for the 28-GHz band, implemented in 28nm FD-SOI CMOS technology. The phase control is introduced in an injection-locked oscillator, followed by an injection-locked frequency tripler. The phase of the output signal is compared with that of the input signal using a phase detector based on third harmonic mixing, enabling automatic phase tuning using low frequency detector outputs. Additionally, the phase detector can be used to detect locking of the oscillators, supporting automatic frequency tuning. A 24-30GHz sliding-IF receiver is also implemented to test the LO circuitry. Simulations show that the phase shifter achieves >360° tuning range over the full 24-30GHz span, with a gain variation of 0.11 dB or less, and that the phase detector has an rms phase error of <2.5°. The entire chip, including pads, measures 1080μm x 1080μm and consumes 27-29 mW from a 1 V supply

A 20-GHz Bandwidth Power Amplifier for Phased Array 5G New Radio Transmitters

A 27-47-GHz differential cascode power amplifier for millimeter-wave 5G new radio applications is presented. The PA is a three-stage design using inductively coupled impedance transformers with 31-dB nominal power gain. A device periphery ratio of 1:2:6 is adopted for predriver, driver, and final stage, respectively. A gain equalization technique was used in the interstage transformers to obtain the required bandwidth with high gain flatness. To enable the use of 2.7-V supply, a cascode topology was employed in all three stages. A small signal gain of 31 dB was achieved with a 3-dB bandwidth of 20 GHz, equivalent to a 54% fractional bandwidth centered at 37 GHz. A saturated output power of 20.6 dBm was measured at 38.5 GHz. With a 100-MHz 64-QAM OFDM modulated signal at 37 GHz and at EVM =-25 dB, an output power of 11.6 dBm and an ACLR1 of-32/-30.8 dBc were obtained. An SiGe HBT BiCMOS process with f_{\mathrm{ MAX}} = 330 GHz was used for fabrication. The PA has an active area of 0.28 mm2 and is measured to a best in class FOM of 94.7 dB

A Decade Frequency Range CMOS Power Amplifier for Sub-6-GHz Cellular Terminals

A wideband 65-nm CMOS power amplifier (PA) is presented, with a decade frequency range from 600 MHz to 6.0 GHz. In this frequency range, the output power exceeds 26.6 dBm and the power gain and power-added efficiency (PAE) exceed 18.1 dB and 49%, respectively. For a 7.5-dB peak-to-average-power-ratio (PAPR) long term evolution (LTE) signal at 1.9 GHz, the circuit provides an average output power of 19 dBm, with a PAE of 40%, and an adjacent channel leakage ratio (ACLR) exceeding -31 dBc. In LTE measurements at 5.9 GHz, the average output power, PAE, and ACLR are 18.5 dBm, 38.8%, and -30 dBc, respectively, using supply modulation and baseband predistortion. The wide bandwidth (BW) and high performance are achieved by introducing a dual output topology with an off-chip higher order output-matching network, combined with a positive feedback cross-coupled differential cascode amplifier stage. By using supply modulation and dynamic gate bias with an injection-locked PA, improved back-off efficiency, and acceptable out-of-band and in-band distortion is obtained. The integrated circuit occupies an area of 1.0 \times 0.73 mm2 in standard 65-nm CMOS technology and uses a supply of 3.0 V

Comparative Analysis of Switching Performance of Transistors in SOS process for RF Applications

Silicon-on-sapphire (SOS) technology is gaining rapid ground in RF applications due to its inherent low parasitic capacitance and the availability of high Q passive components. In this paper, performance of different transistors in SOS technology for switching applications has been verified. Quality factor, OFF performance, and harmonic distortion of all N-types transistors have been simulated and a comparative analysis is provided. Based on this analysis it can be concluded that for the same W/L ratio, NL and IN transistors in the FC process give higher quality factor and also higher C on/C off, while in the GC process, IN devices perform best