Relaxed Half-Stochastic Belief Propagation

Low-density parity-check codes are attractive for high throughput applications because of their low decoding complexity per bit, but also because all the codeword bits can be decoded in parallel. However, achieving this in a circuit implementation is complicated by the number of wires required to exchange messages between processing nodes. Decoding algorithms that exchange binary messages are interesting for fully-parallel implementations because they can reduce the number and the length of the wires, and increase logic density. This paper introduces the Relaxed Half-Stochastic (RHS) decoding algorithm, a binary message belief propagation (BP) algorithm that achieves a coding gain comparable to the best known BP algorithms that use real-valued messages. We derive the RHS algorithm by starting from the well-known Sum-Product algorithm, and then derive a low-complexity version suitable for circuit implementation. We present extensive simulation results on two standardized codes having different rates and constructions, including low bit error rate results. These simulations show that RHS can be an advantageous replacement for the existing state-of-the-art decoding algorithms when targeting fully-parallel implementations

On the dynamics of continuous-time analog iterative decoding

Iterative decoding with flooding schedule can be formulated as a fixed-point problem solved iteratively by successive substitution (SS) method. la this work, we model continuous-time analog (asynchronous) iterative decoding by a first-order differential equation, and show that it can be approximated as the application of the well-known successive over relaxation (SOR) method for solving the fixed-point problem. Simulation results for belief propagation (sum-product) and min-sum algorithms confirm that SOR, which is in general superior to the simpler SS method, can considerably improve the performance of iterative decoding for short codes. The improvement in performance increases with the maximum number of iterations and by reducing the step size in SOR, and the asymptotic result, corresponding to infinite maximum number of iterations and infinitesimal step size represents the performance of continuous-time analog iterative decoding. This means that under ideal circumstances continuous-time analog decoders can outperform their discrete-time digital counterparts by a large margin. Moreover, the results obtained by the proposed model are surprisingly close to the results of circuit simulation of a min-sum analog decoder presented in [1]. Our work also suggests a general framework for improving iterative decoding algorithms on graphs with cycles, even for synchronous digital implementations

Iterative Decoding in Analog CMOS

In this paper, a novel current-mode approach is proposed for implementing basic building blocks of an analog iterative decoder. The decoder is based on the so-called min-sum algorithm (also referred to as max-sum or max-product) and can be used to decode powerful coding schemes such as low-density paritycheck (LDPC) codes and turbo codes. The proposed circuits can be implemented by standard CMOS technology, which means lower fabrication cost and/or simpler design compared to previously reported analog iterative decoders that are based on BiCMOS or sub-threshold CMOS technology. To demonstrate the functionality of the proposed design, simulation results based o

Comparison between continuous-time asynchronous and discrete-time synchronous iterative decoding

Conventional iterative decoding with flooding or parallel schedule can be formulated as a fixed-point problem solved iteratively by successive substitution (SS) method In this work, we investigate the dynamics of continuous-time asynchronous analog implementation of iterative decoding, and show that it can be approximated as the application of the well-known successive over relaxation (SOR) method for solving the fixed-point problem. We observe that SOR with the optimal relaxation factor can considerably improve the performance of iterative decoding for short low-density parity-check (LDPC) codes compared to SS. Our simulation results for the application of SOR to belief propagation (sum-product) and min-sum algorithms demonstrate improvements of up to about 0.7 dB over the standard SS for randomly constructed LDPC codes. The improvement in performance increases with the maximum number of iterations and by accordingly reducing the relaxation factor. The asymptotic result, corresponding to infinite maximum number of iterations and infinitesimal relaxation factor represents the performance of analog continuous-time asynchronous iterative decoding. This means that under ideal circumstances continuous-time asynchronous analog decoders can outperform their discrete-time synchronous digital counterparts by a large margin. The proposed model for analog decoding, and the associated performance curves, can be used as an "ideal analog decoder" benchmark for performance evaluation of analog decoding circuits

Iterative decoding in analog CMOS

In this paper, a novel current-mode approach is proposed for implementing basic building blocks of an analog iterative decoder. The decoder is based on the so-called min-sum algorithm (also referred to as max-sum or max-product) and can be used to decode powerful coding schemes such as low-density parity-check (LDPC) codes and turbo codes, The proposed circuits can be implemented by standard CMOS technology, which means lower fabrication cost and/or simpler design compared to previously reported analog iterative decoders that are based on BiCMOS or sub-threshold CMOS technology. To demonstrate the functionality of the proposed design, simulation results based on TSMC 0.18μm CMOS technology for a (7,4) Hamming code are also presented

Dynamics and performance analysis of analog iterative decoding for low-density parity-check (LDPC) codes

Conventional iterative decoding with flooding or parallel schedule can be formulated as a fixed-point problem solved iteratively by a successive substitution (SS) method. In this paper, we investigate the dynamics of a continuous-time (asynchronous) analog implementation of iterative decoding, and show that it can be approximated as the application of the well-known successive relaxation (SR) method for solving the fixed-point problem. We observe that SR with the optimal relaxation factor can considerably improve the error-rate performance of iterative decoding for short low-density parity-check (LDPC) codes, compared with SS. Our simulation results for the application of SR to belief propagation (sum-product) and min-sum algorithms demonstrate improvements of up to about 0.7 dB over the standard SS for randomly constructed LDPC codes. The improvement in performance increases with the maximum number of iterations, and by accordingly reducing the relaxation factor. The asymptotic result, corresponding to an infinite maximum number of iterations and infinitesimal relaxation factor, represents the steady-state performance of analog iterative decoding. This means that under ideal circumstances, continuous-time (asynchronous) analog decoders can outperform their discrete-time (synchronous) digital counterparts by a large margin. Our results also indicate that with the assumption of a truncated Gaussian distribution for the random delays among computational modules, the error-rate performance of the analog decoder, particularly in steady state, is rather independent of the variance of the distribution. The proposed simple model for analog decoding, and the associated performance curves, can be used as an "ideal analog decoder" benchmark for performance evaluation of analog decoding circuits