Energy Efficient Image/Video Data Transmission on Commercial Multi-Core Processors

sensor

Worst case eye estimation method considering power noise on Tx output driver and channel crosstalk & ISI in interposer-based 2.5D interfaces

Worst case eye estimation method considering the power noise on Tx output driver and the crosstalk of the interposer channel in interposer-based 2.5D interfaces is proposed. For the eye estimation, the estimation of the output response is preceded, considering the characteristics of Tx output driver and interposer channel. The worst case eye diagram is estimated through the definition of the worst bit patterns ('1' & '0') and worst ISI data sets when the power noise on the Tx output driver and the channel crosstalk are considered, respectively. The eye estimation method is validated by comparison with HSPICE simulation. This estimation method allows for the efficient simulation and reliable accuracy

Mechanistic insights into the simultaneous removal of As(V) and Cr(VI) oxyanions by a novel hierarchical corolla-like MnO2-decorated porous magnetic biochar composite: A combined experimental and density functional theory study

A novel hierarchical corolla-like MnO2-decorated porous magnetic biochar composite (c-PMB/MnO2) was synthesized and used for the removal of As(V) and Cr(VI) from aqueous solutions. The experimental results indicated that the adsorption affinity order of c-PMB/MnO2 in the single-component system was As(V) (0.414 mmol/g) < Cr(VI) (0.421 mmol/g), whereas it was reversed in the binary-component system as As(V) (0.446 mmol/g) >> Cr (VI) (0.185 mmol/g), which were more pronounced in sequential adsorption systems. XPS results revealed that all components of c-PMB/MnO2 (i.e., Fe3O4, MnO2, and biochar) contributed to As(V) and Cr(VI) adsorption, while the selective reduction of adsorbed Cr(VI) to Cr(III) occurred via the redox reaction between Fe3O4 and Cr (VI). Density functional theory calculations further indicated that As(V) and Cr(VI) compete for the available binding sites in binary-component system, although the presence of reduced Cr(III) as a majority species serves as a strong binding site for As(V) via the formation of covalent bonding between Cr(III) and the O atom in As(V) with binding energies of - 123.1 and - 125.6 kcal/mol, thereby enhancing competitive As(V) adsorption in binary-component and sequential adsorption systems. These results may provide important information to better understand the competitive adsorption mechanisms for the simultaneous removal of As(V) and Cr(VI) in water

Signal Integrity Design of Bump-Less Interconnection for High-Speed Signaling in 2.5D and 3D IC

With the advent of 2.5D and 3D IC, micro bumps has been highlighted as the core technology for realization of 2.5D and 3D IC. However, due to the difficulties about fabrication of reliable and cost-effective micro bumps, resulting in decrease in the final chip yield. In this paper, we propose a bump-less interconnection for high-speed signaling in 2.5D and 3D IC. In the proposed interconnection, high speed signal is transmitted via coupling pads instead of micro bumps. Signal integrity of the proposed interconnection is analyzed by simulation in the frequency- and time-domain. For a more detailed analysis, the proposed interconnection and the interconnection with the micro bumps are compared. In addition, because the silicon, organic and glass interposer have been widely employed for the 2.5D and 3D IC packaging, signal integrity of the proposed interconnection on three types of the interposer is compared and analyzed

Analysis of On-chip Low-Dropout Regulator Induced PDN Noise at High-speed Output Buffer

This study analyzes on-chip PDN noise induced by on-chip LDO regulator at high-speed buffer. On-chip PDN noise induced by on-chip LDO regulator is considerably dependent on the speed and input sequence of the output buffer. Off-chip power noise has negligible impact on noise induced by on-chip LDO regulator due to the inherent LDO circuit characteristic. Feedback noise, on-chip LDO circuit parameters, and off-chip ground design dominantly determine the noise and jitter in a different way. Finally, this study proposes the useful design guidance for reducing PDN noise and output jitter induced by on-chip LDO regulator at high-speed buffer

Modeling and Analysis of a Power Distribution Network in TSV-Based 3-D Memory IC Including P/G TSVs, On-Chip Decoupling Capacitors, and Silicon Substrate Effects

In this paper, we propose a model for 3-D stacked on-chip power distribution networks (PDNs) in through silicon via (TSV)-based 3-D memory ICs that includes the effects of power/ground TSVs (P/G TSVs), on-chip decoupling capacitors (on-chip decaps), and the silicon substrate. In the modeling procedure of 3-D stacked on-chip PDNs, the distributed RLGC-lumped model of an on-chip PDN, including the effects of the on-chip decaps and silicon substrate, is proposed. Additionally, the RLGC-lumped model of a P/G TSV pair is introduced. The proposed model of the 3-D stacked on-chip PDN combines the proposed models of on-chip PDNs with the models of P/G TSV pairs in a hierarchical order with a segmentation method. The proposed models of the on-chip PDN and 3-D stacked on-chip PDN are successfully validated by simulations and measurements up to 20 GHz. Additionally, with these models, the impedances of the 3-D stacked on-chip PDNs are analyzed with respect to the variations in the number of P/G TSV pairs, the capacitance of on-chip decaps, and the height of an interlayer dielectric layer between the on-chip PDN and silicon substrate. These variations critically affect the impedance of the 3-D stacked on-chip PDN by changing the capacitance and inductance of the PDN

Design of On-Chip Linear Voltage Regulator Module And Measurement of Power Distribution Network Noise Fluctuation at High-Speed Output Buffer

By applying on-chip linear VRM, PDN inductance is greatly decreased and PDN resonance peak disappears, which is usually generated by PCB/PKG inductance and on-chip capacitance. To confirm, we design an application circuits which have on-chip linear voltage regulator module (VRM) with aggressor and victim buffer. We validate the advantages of on-chip linear VRM by measuring fabricated chip in this research. Moreover, we show PDN self-impedance at output buffer by simulation with designed PCB's S-parameter, and eye-diagram power fluctuation up to 1 Gbps

Lumbar Spine Computed Tomography to Magnetic Resonance Imaging Synthesis Using Generative Adversarial Network: Visual Turing Test

(1) Introduction: Computed tomography (CT) and magnetic resonance imaging (MRI) play an important role in the diagnosis and evaluation of spinal diseases, especially degenerative spinal diseases. MRI is mainly used to diagnose most spinal diseases because it shows a higher resolution than CT to distinguish lesions of the spinal canals and intervertebral discs. When it is inevitable for CT to be selected instead of MR in evaluating spinal disease, evaluation of spinal disease may be limited. In these cases, it is very helpful to diagnose spinal disease with MR images synthesized with CT images. (2) Objective: To create synthetic lumbar magnetic resonance (MR) images from computed tomography (CT) scans using generative adversarial network (GAN) models and assess how closely the synthetic images resembled the true images using visual Turing tests (VTTs). (3) Material and Methods: Overall, 285 patients aged ≥ 40 years who underwent lumbar CT and MRI were enrolled. Based on axial CT and T2-weighted axial MR images from 285 patients, an image synthesis model using a GAN was trained using three algorithms (unsupervised, semi-supervised, and supervised methods). Furthermore, VTT to determine how similar the synthetic lumbar MR images generated from lumbar CT axial images were to the true lumbar MR axial images were conducted with 59 patients who were not included in the model training. For the VTT, we designed an evaluation form comprising 600 randomly distributed axial images (150 true and 450 synthetic images from unsupervised, semi-supervised, and supervised methods). Four readers judged the authenticity of each image and chose their first- and second-choice candidates for the true image. In addition, for the three models, structural similarities (SSIM) were evaluated and the peak signal to noise ratio (PSNR) was compared among the three methods. (4) Results: The mean accuracy for the selection of true images for all four readers for their first choice was 52.0% (312/600). The accuracies of determining the true image for each reader’s first and first + second choices, respectively, were as follows: reader 1, 51.3% and 78.0%; reader 2, 38.7% and 62.0%, reader 3, 69.3% and 84.0%, and reader 4, 48.7% and 70.7%. In the case of synthetic images chosen as first and second choices, supervised algorithm-derived images were the most often selected (supervised, 118/600 first and 164/600 second; semi-supervised, 90/600 and 144/600; and unsupervised, 80/600 and 114/600). For image quality, the supervised algorithm received the best score (PSNR: 15.987 ± 1.039, SSIM: 0.518 ± 0.042). (5) Conclusion: This was the pilot study to apply GAN to synthesize lumbar spine MR images from CT images and compare training algorithms of the GAN. Based on VTT, the axial MR images synthesized from lumbar CT using GAN were fairly realistic and the supervised training algorithm was found to provide the closest image to true images