Design & Development of a Robotic System Using LEGO Mindstorm

This research presents a design and development of robotic system based on LEGO Mindstorm kit. The system is capable in operating an off-line programming method, starting from its programming sequences until robotic implementation of the program. During early stages, the research is emphasis more towards designing a robotic system using RoboLab software and C++ programming language. A robotic hardware system has been developed using LEGO Mindstorm kit. The robotic model acts as a prototype or test-bed for programming execution. The model involves motorize movement, sensors detection and machine vision to be manipulated by the programmers inside their programs. Since the model is built using LEGO bricks, the model is fully customized, in term of its applications, to perform any relevant tasks. Ultimately, the algorithm development program designed earlier is linked up directly to the robotic model for program implementation and verification. For this research, several set of robots by using Lego has been developed and it uses LeJos and C programming techniques as a platform. A Java-based robot development tool has been set up as alternative programming methods incorporating LeJos and the controller. A prototype of a mobile robot based on Lego successfully implemented by using PIC and can be controlled through voice recognition

8-channel logic analyzer controller design FPGA work in progress

This paper presents a Field Programmable Gate Array (FPGA) based logic analyzer controller. The controller circuit is capable of performing data acquisition and signal display on a 600x480 VGA monitor. The controller was designed using Very High Speed Integrated Circuit Hardware Description Language (VHDL) coding and schematic capture. For validation, behavioral simulations are carried out using Xilinx ISE simulator. The synthesis of the controller onto Xilinx Spartan XC3S200-4FT256 FPGA chip is also presented. The motivation of this project is to explore the capability of designing a complete digital system in a single FPGA chip

Implementing digital finite impulse response filter using FPGA

This paper describes the design of Transposed Form FIR filter implemented in the Spartan-II and Virtex-E family of FPGAs. The design is an 8-tap filter based on 16-bit input samples and 14-bit signed coefficients.The basic building blocks of the filter are KCMs, Adders, Registers, and a delay-locked loop.All the 14-bit coefficient factors are stored with an 18-bit word size in the ROM.The program is written in VHDL source code based on application Xilinx notes [1] that describe the design of an FIR filter.The software tools have been used are Xilinx ISE Webpack 8.1, ModelSim 6.1e and Matlab 7.0

Modeling and Simulation of Finite State Machine Memory Built-In Self Test Architecture for Embedded Memories

Memory Built-in Self Test (MBIST) or as some refer to it array as built-in self-test is an amazing piece of logic. Without any (direct) connection to the outside world, a very complex embedded memory can be tested efficiently, easily and at lower cost. Modeling and simulation of Finite State Machine (FSM) MBIST is presented in this paper. The design architecture is written using Very High Speed Integrated Circuit Hardware Description Language (VHDL) code using Xilinx ISE tools. The architecture is modeled and synthesized using register transfer level (RTL) abstraction. Verification of this architecture is carried out by testing stuckat-faults SRAM. Two BIST algorithms are implemented, i.e., MATS and March C- to test the faulty SRA

A Low Profile Switchable Pattern Directivity Antenna using Circular Sectorized EBG

In this paper, a low profile patch antenna switchable radiation pattern diversity with total thickness o

Redundant Residue Number System Code for Fault-Tolerant Hybrid Memories

Hybrid memories are envisioned as one of the alternatives to existing semiconductor memories. Although offering enormous data storage capacity, low power consumption, and reduced fabrication complexity (at least for the memory cell array), such memories are subject to a high degree of intermittent and transient faults leading to reliability issues. This article examines the use of Conventional Redundant Residue Number System (C-RRNS) error correction code, which has been extensively used in digital signal processing and communication, to detect and correct intermittent and transient cluster faults in hybrid memories. It introduces a modified version of C-RRNS, referred to as 6M-RRNS, to realize the aims at lower area overhead and performance penalty. The experimental results show that 6M-RRNS realizes a competitive error correction capability, provides larger data storage capacity, and offers higher decoding performance as compared to C-RRNS and Reed-Solomon (RS) codes. For instance, for 64-bit hybrid memories at 10% fault rate, 6MRRNS has 98.95% error correction capability, which is 0.35% better than RS and 0.40% less than C-RRNS. Moreover, when considering 1Tbit memory, 6M-RRNS offers 4.35% more data storage capacity than RS and 11.41% more than C-RRNS. Additionally, it decodes up to 5.25 times faster than C-RRNS

On Defect Oriented Testing for Hybrid CMOS/memristor Memory

Hybrid CMOS/memristor memory (hybrid memory) technology is one of the emerging memory technologies potentially to replace conventional non-volatile flash memory. Existing research on such novel circuits focuses mainly on the integration between CMOS and non-CMOS, fabrication techniques and reliability improvement. However, research on defect analysis for yield and quality improvement is still in its infancy stage. This paper presents a framework of defect oriented testing in hybrid memory based on electrical simulation. First, a classification and definition of defects is introduced. Second, a simulation model for defect injection and circuit simulation is proposed. Third, a case study to illustrate how the proposed approach can be used to analyze the defects and translate their electrical faulty behavior into fault models - in order to develop the appropriate tests and design for testability schemes - is provided. The simulation results show that in addition to the occurrence of conventional semiconductor memories faults, new unique faults take place, e.g., faults that cause the cell to hold an undefined state. These new unique faults require new test approaches (e.g., DfT) in order to be able to detect them

Cost-Efficient Fault-Tolerant Decoder for Hybrid Nanoelectronic Memories

Existing work on fault tolerance in hybrid nanoelectronic memories (hybrid memories) assumes that faults only occur in the memory array and the encoder, not in the decoder. However, as the decoder is structured using scaled CMOS devices, it is also becoming vulnerable to faults. This paper presents a cost-efficient fault-tolerant decoder for hybrid memories that are impacted by a high degree of non-permanent clustered faults. Fault-tolerant capability is achieved by combining partial hardware redundancy scheme and on-line masking scheme based on Muller C-gates. In addition, the cost-efficient implementation of the decoder is realized by modifying the decoding sequence and implementing it based on time redundancy. Experimental results show that the proposed decoder is able to provide better reliability of the overall hybrid memory system, yet requires smaller area as compared to conventional decoder. For example, when assuming the fault ratio between decoder and memory array is 1:10 and at 10% fault rate, the proposed decoder ensures 1% higher reliability of the overall hybrid memory system. Moreover, the proposed decoder realizes 18.4% smaller area overhead for 64-bit word hybrid memory