Work-in-Progress: Determining MPSoC Layout from Thermal Camera Images

In many safety-critical applications, Multi-Processor Systems-on- Chip (MPSoC) must operate within a given thermal envelope under harsh environmental conditions. Meeting the thermal requirements often requires using advanced task allocation and scheduling techniques that are guided by detailed power models. This paper introduces a method that has the potential to simplify the creation of such models. It constructs so-called heat maps from thermal camera images. By comparing the heat maps of different workloads, we identify the locations of on-chip components and the amount of heat produced by them. We demonstrate our method on the i.MX8QuadMax chip from NXP, where we identify the locations of CPU clusters, bigger CPU cores, GPUs, and DRAM controllers

Control Performance Optimization for Application Integration on Automotive Architectures

Automotive software implements different functionalities as multiple control applications sharing common platform resources. Although such applications are often developed independently, the control performance of the resulting system depends on how these applications are integrated. A key integration challenge is to efficiently schedule these applications on shared resources with minimal control performance degradation. We formulate this problem as that of scheduling multiple distributed periodic control tasks that communicate via messages with non-zero jitter. The optimization criterion used is a piecewise linear representation of the control performance degradation as a function of the end-to-end latency of the application. The three main contributions of this article are: 1) a constraint programming (CP) formulation to solve this integration problem optimally on time-triggered architectures; 2) an efficient heuristic called Flexi ; and 3) an experimental evaluation of the scalability and efficiency of the proposed approaches. In contrast to the CP formulation, which for many real-life problems might have unacceptably long running times, Flexireturns nearly optimal results (0.5 percent loss in control performance compared to optimal) for most problems with more acceptable running times

Comparison between Laying Hen Performance in the Cage System and the Deep Litter System on a Diet Free from Animal Protein

Battery cage systems for housing laying hens are being replaced by alternative systems including the deep litter system. At the same time, the substitution of meat and bone meal by vegetable matter in poultry feed mixtures is sought in the nutrition of laying hens. In the experiment, we compared the performance of laying hens of the ISA BROWN hybrid in both the cage system and the deep litter system, on a diet with the meat and bone meal content replaced by vegetable feeds (based on lupin). In the first group, 36 laying hens were kept in the deep litter system; in the second group, 36 laying hens were kept in cages. Over the period of nine months, the number of eggs laid, their weight, shell quality, the clinical state of the laying hens and incidence of their mortality were monitored daily. We found that in the cage system a higher number of eggs was obtained; a lower mean egg weight (p p p p p &gt; 0.05), and the number of laying hens which died was lower (p < 0.05) in comparison with the deep litter system. The results of the experiment demonstrate that, with the substitution of meat and bone meal by vegetable matter in the feed mixtures for laying hens, there are differences between the performance of laying hens from the deep litter system as compared to the laying hens from the cage system. The deep litter system better meets the requirements for the welfare of laying hens; however, it provides a lower yield

Software Model Checking with Explicit Scheduler and Symbolic Threads

In many practical application domains, the software is organized into a set of threads, whose activation is exclusive and controlled by a cooperative scheduling policy: threads execute, without any interruption, until they either terminate or yield the control explicitly to the scheduler. The formal verification of such software poses significant challenges. On the one side, each thread may have infinite state space, and might call for abstraction. On the other side, the scheduling policy is often important for correctness, and an approach based on abstracting the scheduler may result in loss of precision and false positives. Unfortunately, the translation of the problem into a purely sequential software model checking problem turns out to be highly inefficient for the available technologies. We propose a software model checking technique that exploits the intrinsic structure of these programs. Each thread is translated into a separate sequential program and explored symbolically with lazy abstraction, while the overall verification is orchestrated by the direct execution of the scheduler. The approach is optimized by filtering the exploration of the scheduler with the integration of partial-order reduction. The technique, called ESST (Explicit Scheduler, Symbolic Threads) has been implemented and experimentally evaluated on a significant set of benchmarks. The results demonstrate that ESST technique is way more effective than software model checking applied to the sequentialized programs, and that partial-order reduction can lead to further performance improvements.Comment: 40 pages, 10 figures, accepted for publication in journal of logical methods in computer scienc

Parallel Algorithm for Feedforward Neural Network Controller

A problem with simulation of multilayer neural network on transputer array is described in this article. The decomposition and mapping on given architecture is proposed as well as a simple message passing scheme. Practical experiments with inverted pendulum plant are described including useful hints for setting neural network architecture and tuning neural networks parameters. Then neural controller is designed and criterion function is defined for given control problem. Finally the real-time aspects of the controller design are outlined

Time-Sensitive-Aware Scheduling Traffic (TSA-ST) Algorithm in Software-Defined Networking

Time-sensitive-aware scheduling traffic system is capable to eliminate the queuing delay in the network that resulting hard real-time guarantees. Hence, this article aims to develop a time-sensitive-aware scheduling traffic system which is able to avoid multiple time-sensitive flows from conducting in the same path simultaneously so that the queueing delay can be eliminated. Under this prologue, an algorithm Time-Sensitive-Aware Scheduling Traffic (TSA-ST) is proposed to reduce the time complexity in the transmission schedule while maintaining the quality of the scheduling system. In the end, the transmission schedule will be computed in different network topologies to evaluate the performance and accuracy

Stock Optimization of a Kanban-based Assembly Line

The objective of this paper is to describe a way to optimize the stock reserves for an existing assembly line where the parts are supplied according to the Kanban-method