Effects of fluorine plasma and ammonia annealing on pentacene thin -film transistor with ZrLaOx as gate dielectric

Pentacene organic thin-film transistor (OTFT) based on ZrLaOx gate dielectric is proposed and has been fabricated. The effects of fluorine plasma and ammonia annealing on the properties of the OTFT have been studied. It reveals that the plasma treatment can greatly improve carrier mobility and shift the threshold voltage in the positive direction. With a threshold voltage less than 0.5 V, the OTFT can work at very low supply voltage. On the other hand, the ensuing ammonia annealing counteracts the plasma treatment and shifts the threshold voltage in the opposite direction. © 2012 IEEE.published_or_final_versio

Improved Performance of Amorphous InGaZnO Thin-Film Transistor with Ta2O5 Gate Dielectric by using La Incorporation

published_or_final_versio

A low-frequency noise model with carrier generation-recombination process for pentacene organic thin-film transistor

published_or_final_versio

High-performance pentacene thin-film transistor with ZrLaO gate dielectric passivated by fluorine incorporation

postprin

High-mobility pentacene OTFT with TaLaO gate dielectric passivated by fluorine plasma

Pentacene thin-film transistor with high-κ TaLaO as gate dielectric has been fabricated and shows a carrier mobility of 0.73 cm2/V s, much higher than that based on pure La2O3 (0.43 cm2/V s) due to the smoother surface of the TaLaO film and thus larger pentacene islands grown on it in the initial stage. Moreover, among various times for fluorine-plasma treatment on the TaLaO gate dielectric, 100 seconds result in the highest carrier mobility of 1.12 cm2/V s due to (1) smoothest oxide surface achieved by fluorine passivation of oxide traps, as measured by AFM and supported by smallest sub-threshold swing and lowest low-frequency noise; (2) the largest pentacene grains grown on the smoothest oxide surface, as demonstrated by AFM. Pentacene islands on on TaLaO or La2O3 gate dielectric with different plasma treatment times.postprin

High-Performance Pentacene Thin-Film Transistor With High-κ HfLaON as Gate Dielectric

published_or_final_versio

High-mobility pentacene thin-film transistor by using LaxTa(1-x)Oy as gate dielectric

Pentacene organic thin-film transistors (OTFTs) using LaxTa(1−x)Oy as gate dielectric with different La contents (x = 0.227, 0.562, 0.764, 0.883) have been fabricated and compared with those using Ta oxide or La oxide. The OTFT with La0.764Ta0.236Oy can achieve a carrier mobility of 1.21 cm2 V−1s−1s, which is about 40 times and two times higher than those of the devices using Ta oxide and La oxide, respectively. As supported by XPS, AFM and noise measurement, the reasons lie in that La incorporation can suppress the formation of oxygen vacancies in Ta oxide, and Ta content can alleviate the hygroscopicity of La oxide, resulting in more passivated and smoother dielectric surface and thus larger pentacene grains, which lead to higher carrier mobility.postprin

Effects of fluorine plasma and ammonia annealing on pentacene thin-film transistor with HfTiO as gate dielectric

Pentacene organic thin-film transistor (OTFT) with high-K HffiO gate dielectric has been fabricated. The effects of fluorine plasma and ammonia annealing on the properties of the OTFT have been studied. After treating the dielectric in the plasma, the carrier mobility of the transistor can be improved by about 5 times to 0.0883 cm2/V•s. Moreover, the fluorine plasma treatment can shift the threshold voltage of the device in the positive direction. Experimental results also show that NH3 annealing can enhance the OTFT performance in terms of higher mobility, smaller sub-threshold slope and larger on/off ratio.published_or_final_versio

Threshold-voltage instability of polymer thin-film transistor under gate-bias and drain-bias stresses

Polymer thin-film transistors (PTFTs) based on MEH-PPV semiconductor are fabricated by spin-coating process and characterized. Gate-bias and drain-bias stress effects at room temperature are observed in the devices. The saturation current decreases and the threshold voltage shifts toward negative direction upon the gate-bias stress. However, the saturation current increases and the threshold voltage shifts toward positive direction upon the drain-bias stress. For variable bias stress conditions, carrier mobility is almost unchanged. The results suggest that the origin of threshold-voltage shift upon negative gate-bias stress is predominantly associated with holes trapped within the SiO 2 gate dielectric or at the SiO 2/Si interface due to hotcarrier emission under high gate-bias stress, while time-dependent charge trapping into the deep trap states in the channel region is responsible for the drain-bias stress effect in the PTFTs. © 2008 IEEE.published_or_final_versio