59 research outputs found

    An FPGA implementation of future video coding 2D transform

    Get PDF

    Clinical and radiological results of oxford phase-3 medial unicompartmental knee arthroplasty

    Get PDF
    PubMed ID: 31832288Purpose The aim of this retrospective study was to investigate the effectiveness of medial unicompartmental knee arthroplasty (UKA) by showing the results of the radiological and clinical outcomes of the patients. Materials and methods Seventy-two knees of 54 patients who underwent UKA between September 2005 and March 2011 for medial knee arthritis with a minimum follow-up of six months were evaluated. Range of motion (ROM), Hospital for Special Surgery (HSS) knee score, Knee Society Score (KSS), and Oxford Knee Score (OKS) were investigated both preoperatively and postoperatively. On the other hand, Oxford radiographic evaluation criteria were used to evaluate prostheses radiologically at the final follow-up. Results The average age was 53.4 years (47 to 79 years). The average follow-up time was 39.8 months (8 to 72 months). There was a significant difference between preoperative and postoperative ROM, HSS, and OKS (p<0.05). Radiologically, there was no sign of arthritis on the unoperated side of the knee or failure of prosthesis detected. Before the operation, the average clinical KSS was 63.2 and improved to 91.4 after the operation. In addition, the average functional KSS was 54.9 before the operation and improved to 86.5 after the operation. The average knee flexion degree was 109.1 before the operation and there was an improvement to 123.6 degrees after the operation. Before the operation, the average HSS score was 67.5 (range, 52 to 75) and improved to 89.9 (range, 85 to 100) at the final control examination. Conclusion This study supports the use of Oxford Phase 3 UKA, which has excellent clinical and radiological results in patients with medial knee arthritis

    An HEVC fractional interpolation hardware using memory based constant multiplication

    Get PDF
    Fractional interpolation is one of the most computationally intensive parts of High Efficiency Video Coding (HEVC) video encoder and decoder. In this paper, an HEVC fractional interpolation hardware using memory based constant multiplication is proposed. The proposed hardware uses memory based constant multiplication technique for implementing multiplication with constant coefficients. The proposed memory based constant multiplication hardware stores pre-computed products of an input pixel with multiple constant coefficients in memory. Several optimizations are proposed to reduce memory size. The proposed HEVC fractional interpolation hardware, in the worst case, can process 35 quad full HD (3840×2160) video frames per second. It has up to 31% less energy consumption than original HEVC fractional interpolation hardware

    Novel approximate absolute difference hardware

    Get PDF
    Approximate hardware designs have higher performance, smaller area or lower power consumption than exact hardware designs at the expense of lower accuracy. Absolute difference (AD) operation is heavily used in many applications such as motion estimation (ME) for video compression, ME for frame rate conversion, stereo matching for depth estimation. Since most of the applications using AD operation are error tolerant by their nature, approximate hardware designs can be used in these applications. In this paper, novel approximate AD hardware designs are proposed. The proposed approximate AD hardware implementations have higher performance, smaller area and lower power consumption than exact AD hardware implementations at the expense of lower accuracy. They also have less error, smaller area and lower power consumption than the approximate AD hardware implementations which use approximate adders proposed in the literature

    Novel approximate absolute difference hardware

    Get PDF

    An efficient FPGA implementation of HEVC intra prediction

    Get PDF
    Intra prediction algorithm used in High Efficiency Video Coding (HEVC) standard has very high computational complexity. In this paper, an efficient FPGA implementation of HEVC intra prediction is proposed for 4×4, 8×8, 16×16 and 32×32 angular prediction modes. In the proposed FPGA implementation, one intra angular prediction equation is implemented using one DSP block in FPGA. The proposed FPGA implementation, in the worst case, can process 55 Full HD (1920×1080) video frames per second. It has up to 34.66% less energy consumption than the original FPGA implementation of HEVC intra prediction. Therefore, it can be used in portable consumer electronics products that require a real-time HEVC encoder

    Efficient multiple constant multiplication using DSP blocks in FPGA

    Get PDF
    Multiple constant multiplication (MCM) operation multiplies an input variable with multiple constants. MCM operations are widely used in many applications such as video processing and compression. In this paper, a method is proposed for efficient implementation of MCM operations using DSP blocks in Xilinx FPGAs. The proposed method reduces number of DSP blocks used for implementing a given MCM operation by manipulating the multiple constants used in this MCM operation. In this paper, a high level synthesis tool implementing the proposed method is also proposed. The proposed tool takes the input variable bit length and multiple constants as inputs, and generates a Verilog RTL code which efficiently implements this MCM operation using DSP blocks. The proposed method and tool are used for one of the most complex video compression algorithms, HEVC 2D DCT. They reduced number of DSP blocks used in the FPGA implementation of HEVC 2D DCT algorithm by 35.8%

    A low power versatile video coding (VVC) fractional interpolation hardware

    Get PDF
    Fractional interpolation in Versatile Video Coding (VVC) standard has much higher computational complexity than fractional interpolation in previous video compression standards. In this paper, a low power VVC fractional interpolation hardware is designed and implemented using Verilog HDL. The proposed hardware is the first VVC fractional interpolation hardware in the literature. It interpolates necessary fractional pixels for 1/16 pixel accuracy for all prediction unit sizes. The proposed VVC fractional interpolation hardware, in the worst case, can process 40 full HD (1920x1080) frames per second. It has up to 17% less power consumption than original VVC fractional interpolation hardware
    corecore