Novel image enhancement technique using shunting inhibitory cellular neural networks

This paper describes a method for improving image quality in a color CMOS image sensor. The technique simultaneously acts to compress the dynamic range, reorganize the signal to improve visibility, suppress noise, identify local features, achieve color constancy, and lightness rendition. An efficient hardware architecture and a rigorous analysis of the different modules are presented to achieve high quality CMOS digital camera

A 96 x 64 Intelligent digital pixel array with extended binary stochastic arithmetic

A chip architecture that integrates an optical sensor and a pixel level processing element based on binary stochastic arithmetic is proposed. The optical sensor is formed by an array of fully connected pixels, and each pixel contains a sensing element and a Pulse Frequency Modulator (PFM) converting the incident light to bit streams of identical pulses. The processing element is based on binary stochastic arithmetic to perform signal processing operations on the focal plane VLSI circuit. A 96 x 64 CMOS image sensor is fabricated using 0.5pm CMOS technology and achieves 29 x 29pm pixel size at 15% fill factor

Digital implementation of Shunting Inhibitory Cellular Neural Network

Shunting inhibition is a model of early visual processing which can provide contrast and edge enhancement, and dynamic range compression. An architecture of digital Shunting Inhibitory Cellular Neural Network (SICNN) for real time image processing is presented. The proposed architecture is intended to be used in a complete vision system for edge detection and image enhancement. The present hardware architecture, is modeled and simulated in VHDL. Simulation results show the functional validity of the proposed architecture