21 research outputs found

    A Low-Power RRAM Memory Block for Embedded, Multi-Level Weight and Bias Storage in Artificial Neural Networks

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    Pattern recognition as a computing task is very well suited for machine learning algorithms utilizing artificial neural networks (ANNs). Computing systems using ANNs usually require some sort of data storage to store the weights and bias values for the processing elements of the individual neurons. This paper introduces a memory block using resistive memory cells (RRAM) to realize this weight and bias storage in an embedded and distributed way while also offering programming and multi-level ability. By implementing power gating, overall power consumption is decreased significantly without data loss by taking advantage of the non-volatility of the RRAM technology. Due to the versatility of the peripheral circuitry, the presented memory concept can be adapted to different applications and RRAM technologies

    A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells

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    In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9

    1. Memristor-Symposium 2023

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    The 1.Memristor-Symposium was held from 27-28.02.2023 in Bamberg. Young scientists and PhD students presented their research and covered several topics regarding ongoing memristive research in Germany. Several talks on the topic of memristive devices, their testing, modeling and usage were presented and discussed, covering the whole vertical integration from material and divice up to application level.Das 1.Memristor-Symposium fand am 27. und 28.02.2023 in Bamberg statt. Junge Wissenschaftler*innen und Doktorant*innen präsentierten dort ihre aktuelle Arbeit und deckten dabei mehrere Themengebiete aus der memristiven Forschung in Deutschland ab. Die Vorträge kommen aus dem Bereich der memristiven Bauteile, deren Test, Modellierung und Anwendung und decken dabei die volle vertikale Integration von Materialforschung über Bauteile bis hin zur Anwendungsebene ab

    SiCer: Meeting the Challenges of Tomorrow's Complex Electronic Systems [From the Guest Editors' Desk]

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    Area-efficient fully integrated dual-band class-E/F power amplifier with switchable output power for a BPSK/OOK transmitter

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    This paper presents a novel dual-band class-E/F power amplifier (PA) with switchable output power. It is targeted to work in a BPSK/OOK transmitter in smart facility applications like an autarkic asset-tracking system based on small sensor nodes. The amplifier is fully-integrated and able to operate at both 434MHz and 868MHz without the need for additional inductors, making the design very area-efficient. The output power settings at 868MHz are controllable between -1.79dBm and -24.61dBm at 4.96mA and 1.43mA current consumption, respectively. The whole circuit including all inductors and the matching network in front of the antenna consumes only 0.9mm2 chip area and is fully integrated in a 180nm CMOS process together with a VCO and a PLL

    Enhancing RF bulk acoustic wave devices: multiphysical modeling and performance

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    Nonlinear finite element calculations of layered SAW resonators

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    In this work the nonlinear behavior of layered surface acoustic wave (SAW) resonators is studied with the help of finite element (FE) computations. The full calculations depend strongly on the availability of accurate tensor data. While there are accurate material data for linear computations, the complete sets of higher-order material constants, needed for nonlinear simulations, are still not available for relevant materials. To overcome this problem, scaling factors were used for each available nonlinear tensor. The approach here considers piezoelectricity, dielectricity, electrostriction, and elasticity constants up to the fourth order. These factors act as a phenomenological estimate for incomplete tensor data. Since no set of fourth-order material constants for LiTaO3 is available, an isotropic approximation for the fourth-order elastic constants was applied. As a result, it was found that the fourth-order elastic tensor is dominated by one-fourth order Lamé constant. With the help of the FE model, derived in two different, but equivalent ways, we investigate the nonlinear behavior of a SAW resonator with a layered material stack. The focus was set to third-order nonlinearity. Accordingly, the modeling approach is validated using measurements of third-order effects in test resonators. In addition, the acoustic field distribution is analyzed
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