HW/SW-Codesign und High-Level Synthese des Vollraten-Sprach-Transcodierers GSM 06.10

Available from TIB Hannover: RR 7264(96,8) / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekSIGLEDEGerman

A script environment for the HDL advisor evaluation

The objective of our work is the evaluation of the quality of estimations given by the HDL Advisor. Therefore the estimation step is integrated into the design loop. The integration step itself is described in detail and is mainly based on the computation of the fidelity measure. Our methodology for the evaluation of the quality of the HDL Advisor estimates is to compare the results generated by the HDL Advisor with the characteristics of the (synthesized) designs generated by the Synopsys Design Compiler. The comparison of these design information results in a set of characteristics (e.g., average values, standard deviation, minimum-maximum interval). Furthermore, some additional information is generated which enables the user to identify critical parts of the design. This paper describes an environment for automatic evaluation of the quality of the HDL Advisor based on a user specified set of designs. The environment consists of a set of (C-shell) scripts, which enables a hierarchical proceeding. (orig.)Available from TIB Hannover: RR 7264(96,10) / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekSIGLEDEGerman

Von C nach Hardware: Ein integratives Entwurfskonzept

Available from TIB Hannover: RR 7264(96,3) / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekSIGLEDEGerman

VHE Middleware - Middleware for Virtual Home Environments Schlussbericht

Available from TIB Hannover: F03B536+a / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekSIGLEBundesministerium fuer Bildung und Forschung, Berlin (Germany)DEGerman

Ein Transformations-basiertes Werkzeug fuer die schnelle Analyse und Optimierung eingebetteter Systeme

Available from TIB Hannover: RR 7264(96,1) / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekSIGLEDEGerman

A methodology for rapid analysis and optimization of embedded systems

Available from TIB Hannover: RR 7264(96,2) / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekSIGLEDEGerman

Using the HDL-advisor for shortening the system design loop

In this paper, the integration of RT-level advice into the system-level synthesis methodology is examined. The synthesis procedure starts from a system-level specification given by standard C code. HW is extracted and synthesized by means of high-level synthesis. The result is a structural VHDL description. In order to shorten the design loop in a transformational synthesis environment, the task of conventional RT- and logic-level synthesis inside the optimization loop is replaced by an advice in order to predict the characteristics of the resulting circuit. As experimental results show, this enables the examination of a larger design space by reducing analysis time. (orig.)Available from TIB Hannover: RR 7264(96,6) / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekSIGLEDEGerman

Transformation-based high level design space exploration

This paper describes a methodology for system level design. The starting point is a specification given as standard C program. After a HW/SW-codesign step, design space exploration is performed by examining several versions of the initial design created by means of high-level transformations: Our approach includes an acceleration of the design loop by replacing all tasks of physical design (especially the expensive task of logic synthesis) by a corresponding estimation step. For this, design space exploration can be carried out completely without considering physical design. A complete synthesis process has to be performed once for the only design identified for implementation within the design space exploration phase. The applicability of our methodology is demonstrated by means of an example application, the algorithm for computation of the discrete cosine transformation. (orig.)Available from TIB Hannover: RR 7264(96,9) / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekSIGLEDEGerman