Analytische Modellierung des Zeitverhaltens und der Verlustleistung von CMOS-Gattern

In modernen CMOS-Technologien werden die Verzögerungszeit, die Ausgangsflankensteilheit und der Querstrom eines Gatters sowohl durch die Lastkapazität als auch durch die Steilheit des Eingangssignals beeinflusst. Die heute verwendeten Technologiebibliotheken beinhalten Tabellenmodelle mit 25 oder mehr Stützpunkten dieser Abhängigkeiten, woraus durch Interpolation die benötigten Zwischenwerte berechnet werden. Bisherige Versuche, analytische Modelle abzuleiten beruhten darauf, den Querstrom zu vernachlässigen oder Transistorströme als stückweise linear anzunähern. Der hier gezeigte Ansatz beruht auf einer näherungsweisen Lösung der Differentialgleichung, die aus den beiden Transistorströmen und einer Lastkapazität besteht und damit das Schaltverhalten eines Inverters beschreibt. Mit wenigen Technologieparametern können daraus für einen beliebig dimensionierten Inverter die für eine Timing- und Verlustleistungsanalyse notwendigen Größen berechnet werden. Das Modell erreicht bei einem Vergleich zu Referenzwerten aus SPICE Simulationen eine Genauigkeit von typischerweise 5%.</p><p style=&quot;line-height: 20px;&quot;>In modern CMOS-technologies the gate delay, output transition time and the short-circuit current depend on the capacitive load as well as on the input transition time. Today’s technology libraries use table models with 25 or more samples for these dependencies. Intermediate values have to be calculated through interpolation. Attempts to derive analytical models are based on neglecting the short-circuit current or approximating it by piecewise linear functions. The approach shown in this paper provides an approximate solution for the differential equation describing the dynamic behavor of an inverter circuit. It includes the influence of both transistor currents and a single load capacitance. The required values for timing and power analysis can be calculated with a small set of technology parameters for an arbitrary designed inverter. Compared to reference values extracted from SPICE simulations, the model achieves a typical precision of 5%

Hardwarearchitektur für einen universellen LDPC Decoder

Im vorliegenden Beitrag wird eine universelle Decoderarchitektur für einen Low-Density Parity-Check (LDPC) Code Decoder vorgestellt. Anders als bei den in der Literatur häufig beschriebenen Architekturen für strukturierte Codes ist die hier vorgestellte Architektur frei programmierbar, so dass jeder beliebige LDPC Code durch eine Änderung der Initialisierung des Speichers für die Prüfmatrix mit derselben Hardware decodiert werden kann. Die größte Herausforderung beim Entwurf von teilparallelen LDPC Decoder Architekturen liegt im konfliktfreien Datenaustausch zwischen mehreren parallelen Speichern und Berechnungseinheiten, wozu ein Mapping und Scheduling Algorithmus benötigt wird. Der hier vorgestellte Algorithmus stützt sich auf Graphentheorie und findet für jeden beliebigen LDPC Code eine für die Architektur optimale Lösung. Damit sind keine Wartezyklen notwendig und die Parallelität der Architektur wird zu jedem Zeitpunkt voll ausgenutzt

Linearly polarized GHz magnetization dynamics of spin helix modes in the ferrimagnetic insulator Cu2_{2}OSeO3_{3}

Linear dichroism -- the polarization dependent absorption of electromagnetic waves -- is routinely exploited in applications as diverse as structure determination of DNA or polarization filters in optical technologies. Here filamentary absorbers with a large length-to-width ratio are a prerequisite. For magnetization dynamics in the few GHz frequency regime strictly linear dichroism was not observed for more than eight decades. Here, we show that the bulk chiral magnet Cu$_{2}$OSeO$_{3}$ exhibits linearly polarized magnetization dynamics at an unexpectedly small frequency of about 2 GHz. Unlike optical filters that are assembled from filamentary absorbers, the magnet provides linear polarization as a bulk material for an extremely wide range of length-to-width ratios. In addition, the polarization plane of a given mode can be switched by 90$^\circ$ via a tiny variation in width. Our findings shed a new light on magnetization dynamics in that ferrimagnetic ordering combined with anisotropic exchange interaction offers strictly linear polarization and cross-polarized modes for a broad spectrum of sample shapes. The discovery allows for novel design rules and optimization of microwave-to-magnon transduction in emerging microwave technologies.Comment: 20 pages, 4 figure

A Phenomenological Description of the Non-Fermi-Liquid Phase of MnSi

In order to understand the non-Fermi-liquid behavior of MnSi under pressure we propose a scenario on the basis of the multispiral state of the magnetic moment. This state can describe the recent critical experiment of the Bragg sphere in the neutron scattering which is the key ingredient of the non-Fermi-liquid behavior.Comment: 3 page

Configurable multiplier modules for an adaptive computing system

The importance of reconfigurable hardware is increasing steadily. For example, the primary approach of using adaptive systems based on programmable gate arrays and configurable routing resources has gone mainstream and high-performance programmable logic devices are rivaling traditional application-specific hardwired integrated circuits. Also, the idea of moving from the 2-D domain into a 3-D design which stacks several active layers above each other is gaining momentum in research and industry, to cope with the demand for smaller devices with a higher scale of integration. However, optimized arithmetic blocks in course-grain reconfigurable arrays as well as field-programmable architectures still play an important role. In countless digital systems and signal processing applications, the multiplication is one of the critical challenges, where in many cases a trade-off between area usage and data throughput has to be made. But the a priori choice of word-length and number representation can also be replaced by a dynamic choice at run-time, in order to improve flexibility, area efficiency and the level of parallelism in computation. In this contribution, we look at an adaptive computing system called 3-D-SoftChip to point out what parameters are crucial to implement flexible multiplier blocks into optimized elements for accelerated processing. The 3-D-SoftChip architecture uses a novel approach to 3-dimensional integration based on flip-chip bonding with indium bumps. The modular construction, the introduction of interfaces to realize the exchange of intermediate data, and the reconfigurable sign handling approach will be explained, as well as a beneficial way to handle and distribute the numerous required control signals

Comparison of reconfigurable structures for flexible word-length multiplication

Binary multiplication continues to be one of the essential arithmetic operations in digital circuits. Even though field-programmable gate arrays (FPGAs) are becoming more and more powerful these days, the vendors cannot avoid implementing multiplications with high word-lengths using embedded blocks instead of configurable logic. But on the other hand, the circuit&apos;s efficiency decreases if the provided word-length of the hard-wired multipliers exceeds the precision requirements of the algorithm mapped into the FPGA. Thus it is beneficial to use multiplier blocks with configurable word-length, optimized for area, speed and power dissipation, e.g. regarding digital signal processing (DSP) applications. &lt;br&gt;&lt;br&gt; In this contribution, we present different approaches and structures for the realization of a multiplication with variable precision and perform an objective comparison. This includes one approach based on a modified Baugh and Wooley algorithm and three structures using Booth&apos;s arithmetic operand recoding with different array structures. All modules have the option to compute signed two&apos;s complement fix-point numbers either as an individual computing unit or interconnected to a superior array. Therefore, a high throughput at low precision through parallelism, or a high precision through concatenation can be achieved