Guest Editors' Introduction: Multiprocessor Systems-on-Chips

Single processors may be sufficient for low-performance applications that are typical of early microcontrollers, but an increasing number of applications require multiprocessors to meet their performance goals

Delay Correction in RTL Models of DSP SoC obtained by IP-based design approach

The principal problem of component-based design is that the behavior of the RTL model may be incorrect. This article presents the formalization of the problem and proposes an automatic correction method (called delay correction) to solve it. We propose two algorithms which perform the optimal solution in latency and area. The effectiveness of the approach and the optimality of the proposed solutions are mathematically proven

Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemC

ISBN : 1-4244-0629-3At high abstraction level, Multi-Processor System-On-Chip (SoC) designs are specified as assembling of IP's which can be Hardware or Software. The refinement of communication between these different IP's, known as hardware/software interfaces, is widely seen as the design bottleneck due to their complexity. In order to perform early design validation and architecture exploration, flexible executable models of these interfaces are needed at different abstraction levels. In this paper, we define a unified methodology to implement executable models of the hardware/software interface based on SystemC. The proposed formalism based on the concept of services gives to this approach the flexibility needed for architecture exploration and the ability to be used in automatic generation tools. A case study of hardware/software interface modeling at the Transaction Accurate level is presented. Experimental results show that this method allows higher simulation speed with early performance estimation

An efficient methodology and semi automated flow for design and validation of complex digital signal processing ASICS macro cells

We present a methodology and design flow for signal processing application specific integrated circuit macro-cells. The key features of the methodology are the mastering the complexity of design, the increasing of reuse factor and the early error detection. It takes advantages of a derivative designs, a signal processing modularity, generic modeling and combines both levels of abstraction, in order to produce an efficient architecture. The flow includes a fast verification platform that drives both algorithm and architecture validation in an efficient way. We illustrate the effectiveness of the proposed methodology by a significant industrial application. Experimental design results indicate strong advantages of the proposed schemes