11 research outputs found

    Application of Deterministic Logic BIST on Industrial Circuits

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    We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5%-15%. It is demonstrated that a trade-off is possible between test quality, test time, and silicon area for the BIST hardware. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized

    Object Recognition and Pose Estimation on Embedded Hardware: SURF-Based System Designs Accelerated by FPGA Logic

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    State-of-the-art object recognition and pose estimation systems often utilize point feature algorithms, which in turn usually require the computing power of conventional PC hardware. In this paper, we describe two embedded systems for object detection and pose estimation using sophisticated point features. The feature detection step of the “Speeded-up Robust Features (SURF)” algorithm is accelerated by a special IP core. The first system performs object detection and is completely implemented in a single medium-size Virtex-5 FPGA. The second system is an augmented reality platform, which consists of an ARM-based microcontroller and intelligent FPGA-based cameras which support the main system

    A configurable architecture for the generalized hough transform applied to the analysis of huge aerial images and to traffic sign detection

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    Object recognition in huge image data sets or in live camera images at interactive frame rates is a very demanding task, especially within embedded systems. The recognition task includes the localization of a reference object and its rotation and scaling in a search image. The Generalized Hough Transform (GHT) is known as a powerful and robust technique to support this task by transforming the search image into a 4D parameter space. However, the GHT itself is very complex and demanding towards computational power and memory consumption. This paper presents a novel hardware architecture to perform a complete 4D GHT at interactive frame rates in an FPGA. The architecture is configurable in order to allow a trade-off between performance, accuracy and hardware usage. The proposed architecture has been implemented in a low-cost Zynq-7000 FPGA and successfully evaluated in two practical applications, namely groyne detection in aerial images and traffic sign detection

    Annual Report of the Department of Education, 1939

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    The annual reports of the Newfoundland Department of Education.Titles vary

    A configurable framework for hough-transform-based embedded object recognition systems

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    Real-time object recognition on low-power embedded devices is a widely requested task, needed in manifold applications. However, it is still a demanding challenge to achieve desired performance goals. For example, for advanced driver assistance systems (ADAS) or autonomously driven cars, object recognition and lane detection are indispensable tasks. Another field of application is the continuous retrieval of the construction progress on-site for validation of the construction site status, by detecting installed components using a given CAD model. This paper presents a framework for highly customizable object detection systems implemented on a single heterogeneous computing chip leveraging FPGA logic and standard processors. The FPGA logic is used to implement a custom variation of the Hough Transform and further image processing tasks efficiently. The dedicated logic is supplemented with a software stack, which consists of a Linux operating system, including hardware access drivers, as well as high-level libraries like OpenCV and Robot Operating System (ROS) - all running on the same device. The capabilities of the system are demonstrated for three application scenarios, namely race track recognition, lane recognition and object detection tasks performed within a construction assistance system
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