Artifacts for Calibration of Submicron Width Measurements

Artifacts that are fabricated with the help of molecular-beam epitaxy (MBE) are undergoing development for use as dimensional calibration standards with submicron widths. Such standards are needed for calibrating instruments (principally, scanning electron microscopes and scanning probe microscopes) for measuring the widths of features in advanced integrated circuits. Dimensional calibration standards fabricated by an older process that involves lithography and etching of trenches in (110) surfaces of single-crystal silicon are generally reproducible to within dimensional tolerances of about 15 nm. It is anticipated that when the artifacts of the present type are fully developed, their critical dimensions will be reproducible to within 1 nm. These artifacts are expected to find increasing use in the semiconductor-device and integrated- circuit industries as the width tolerances on semiconductor devices shrink to a few nanometers during the next few years. Unlike in the older process, one does not rely on lithography and etching to define the critical dimensions. Instead, one relies on the inherent smoothness and flatness of MBE layers deposited under controlled conditions and defines the critical dimensions as the thicknesses of such layers. An artifact of the present type is fabricated in two stages (see figure): In the first stage, a multilayer epitaxial wafer is grown on a very flat substrate. In the second stage, the wafer is cleaved to expose the layers, then the exposed layers are differentially etched (taking advantage of large differences between the etch rates of the different epitaxial layer materials). The resulting structure includes narrow and well-defined trenches and a shelf with thicknesses determined by the thicknesses of the epitaxial layers from which they were etched. Eventually, it should be possible to add a third fabrication stage in which durable, electronically inert artifacts could be replicated in diamondlike carbon from a master made by MBE and etching as described above

Silicon sample holder for molecular beam epitaxy on pre-fabricated integrated circuits

The sample holder of the invention is formed of the same semiconductor crystal as the integrated circuit on which the molecular beam expitaxial process is to be performed. In the preferred embodiment, the sample holder comprises three stacked micro-machined silicon wafers: a silicon base wafer having a square micro-machined center opening corresponding in size and shape to the active area of a CCD imager chip, a silicon center wafer micro-machined as an annulus having radially inwardly pointing fingers whose ends abut the edges of and center the CCD imager chip within the annulus, and a silicon top wafer micro-machined as an annulus having cantilevered membranes which extend over the top of the CCD imager chip. The micro-machined silicon wafers are stacked in the order given above with the CCD imager chip centered in the center wafer and sandwiched between the base and top wafers. The thickness of the center wafer is about 20% less than the thickness of the CCD imager chip. Preferably, four titanium wires, each grasping the edges of the top and base wafers, compress all three wafers together, flexing the cantilever fingers of the top wafer to accommodate the thickness of the CCD imager chip, acting as a spring holding the CCD imager chip in place

Innovative Long Wavelength Infrared Detector Workshop Proceedings

The focus of the workshop was on innovative long wavelength (lambda less than 17 microns) infrared (LWIR) detectors with the potential of meeting future NASA and DoD long-duration space application needs. Requirements are for focal plane arrays which operate near 65K using active refrigeration with mission lifetimes of five to ten years. The workshop addressed innovative concepts, new material systems, novel device physics, and current progress in relation to benchmark technology. It also provided a forum for discussion of performance characterization, producibility, reliability, and fundamental limitations of device physics. It covered the status of the incumbent HgCdTe technology, which shows encouraging progress towards LWIR arrays, and provided a snapshot of research and development in several new contender technologies

Growth of III-V films by control of MBE growth front stoichiometry

For the growth of strain-layer materials and high quality single and multiple quantum wells, the instantaneous control of growth front stoichiometry is critical. The process of the invention adjusts the offset or phase of molecular beam epitaxy (MBE) control shutters to program the instantaneous arrival or flux rate of In and As4 reactants to grow InAs. The interrupted growth of first In, then As4, is also a key feature

MBE growth technology for high quality strained III-V layers

The III-V films are grown on large automatically perfect terraces of III-V substrates which have a different lattice constant, with temperature and Group III and V arrival rates chosen to give a Group III element stable surface. The growth is pulsed to inhibit Group III metal accumulation of low temperature, and to permit the film to relax to equilibrium. The method of the invention: (1) minimizes starting step density on sample surface; (2) deposits InAs and GaAs using an interrupted growth mode (0.25 to 2 monolayers at a time); (3) maintains the instantaneous surface stoichiometry during growth (As-stable for GaAs, In-stable for InAs); and (4) uses time-resolved RHEED to achieve aspects (1) through (3)

Correlations between the interfacial chemistry and current-voltage behavior of n-GaAs/liquid junctions

Correlations between the surface chemistry of etched, (100) oriented n-GaAs electrodes and their subsequent photoelectrochemical behavior have been probed by high-resolution x-ray photoelectron spectroscopy. GaAs photoanodes were chemically treated to prepare either an oxide-free near stoichiometric surface, a surface enriched in zero-valent arsenic (As0), or a substrate-oxide terminated surface. The current-voltage (I-V) behavior of each surface type was subsequently monitored in contact with several electrolytes

Method for producing a hybridization of detector array and integrated circuit for readout

A process is explained for fabricating a detector array in a layer of semiconductor material on one substrate and an integrated readout circuit in a layer of semiconductor material on a separate substrate in order to select semiconductor material for optimum performance of each structure, such as GaAs for the detector array and Si for the integrated readout circuit. The detector array layer is lifted off its substrate, laminated on the metallized surface on the integrated surface, etched with reticulating channels to the surface of the integrated circuit, and provided with interconnections between the detector array pixels and the integrated readout circuit through the channels. The adhesive material for the lamination is selected to be chemically stable to provide electrical and thermal insulation and to provide stress release between the two structures fabricated in semiconductor materials that may have different coefficients of thermal expansion

Growth of delta-doped layers on silicon CCD/S for enhanced ultraviolet response

The backside surface potential well of a backside-illuminated CCD is confined to within about half a nanometer of the surface by using molecular beam epitaxy (MBE) to grow a delta-doped silicon layer on the back surface. Delta-doping in an MBE process is achieved by temporarily interrupting the evaporated silicon source during MBE growth without interrupting the evaporated p+ dopant source (e.g., boron). This produces an extremely sharp dopant profile in which the dopant is confined to only a few atomic layers, creating an electric field high enough to confine the backside surface potential well to within half a nanometer of the surface. Because the probability of UV-generated electrons being trapped by such a narrow potential well is low, the internal quantum efficiency of the CCD is nearly 100% throughout the UV wavelength range. Furthermore, the quantum efficiency is quite stable

MBE growth technology for high quality strained III-V layers

III-V films are grown on large automatically perfect terraces of III-V substrates which have a different lattice constant, with temperature and Group II and V arrival rates chosen to give a Group III element stable surface. The growth is pulsed to inhibit Group III metal accumulation to low temperature, and to permit the film to relax to equilibrium. The method of the invention 1) minimizes starting step density on sample surface; 2) deposits InAs and GaAs using an interrupted growth mode (0.25 to 2 mono-layers at a time); 3) maintains the instantaneous surface stoichiometry during growth (As-stable for GaAs, In-stable for InAs); and 4) uses time-resolved RHEED to achieve aspects (1)-14 (3)

Embossed Teflon AF Laminate Membrane Microfluidic Diaphragm Valves

A microfluidic system has been designed to survive spaceflight and to function autonomously on the Martian surface. It manipulates microscopic quantities of liquid water and performs chemical analyses on these samples to assay for the presence of molecules associated with past or present living processes. This technology lies at the core of the Urey Instrument, which is scheduled for inclusion on the Pasteur Payload of the ESA ExoMars rover mission in 2013. Fabrication processes have been developed to make the microfabricated Teflon-AF microfluidic diaphragm pumps capable of surviving extreme temperature excursions before and after exposure to liquid water. Two glass wafers are etched with features and a continuous Teflon membrane is sandwiched between them (see figure). Single valves are constructed using this geometry. The microfabricated devices are then post processed by heating the assembled device while applying pneumatic pressure to force the Teflon diaphragm against the valve seat while it is softened. After cooling the device, the embossed membrane retains this new shape. This solves previous problems with bubble introduction into the fluid flow where deformations of the membrane at the valve seat occurred during device bonding at elevated temperatures (100-150 C). The use of laminated membranes containing commercial Teflon AF 2400 sheet sandwiched between spun Teflon AF 1600 layers performed best, and were less gas permeable than Teflon AF 1600 membranes on their own. Spinning Teflon AF 1600 solution (6 percent in FLOURINERT(Registered TradeMark) FC40 solvent, 3M Company) at 500 rpm for 1.5 seconds, followed by 1,000 rpm for 3 seconds onto Borofloat glass wafers, results in a 10-micron-thick film of extremely smooth Teflon AF. This spinning process is repeated several times on flat, blank, glass wafers in order to gradually build a thick, smooth membrane. After running this process at least five times, the wafer and Teflon coating are heated under vacuum at 220 C for one hour in order to drive off any residual solvent present in the composite film. After this, a second blank, glass wafer is brought down from above and the stack is held under vacuum at 3 atm mechanical pressure for ten 10 hours