727 research outputs found
Scalable Successive-Cancellation Hardware Decoder for Polar Codes
Polar codes, discovered by Ar{\i}kan, are the first error-correcting codes
with an explicit construction to provably achieve channel capacity,
asymptotically. However, their error-correction performance at finite lengths
tends to be lower than existing capacity-approaching schemes. Using the
successive-cancellation algorithm, polar decoders can be designed for very long
codes, with low hardware complexity, leveraging the regular structure of such
codes. We present an architecture and an implementation of a scalable hardware
decoder based on this algorithm. This design is shown to scale to code lengths
of up to N = 2^20 on an Altera Stratix IV FPGA, limited almost exclusively by
the amount of available SRAM
Improved Successive Cancellation Flip Decoding of Polar Codes Based on Error Distribution
Polar codes are a class of linear block codes that provably achieves channel
capacity, and have been selected as a coding scheme for generation
wireless communication standards. Successive-cancellation (SC) decoding of
polar codes has mediocre error-correction performance on short to moderate
codeword lengths: the SC-Flip decoding algorithm is one of the solutions that
have been proposed to overcome this issue. On the other hand, SC-Flip has a
higher implementation complexity compared to SC due to the required
log-likelihood ratio (LLR) selection and sorting process. Moreover, it requires
a high number of iterations to reach good error-correction performance. In this
work, we propose two techniques to improve the SC-Flip decoding algorithm for
low-rate codes, based on the observation of channel-induced error
distributions. The first one is a fixed index selection (FIS) scheme to avoid
the substantial implementation cost of LLR selection and sorting with no cost
on error-correction performance. The second is an enhanced index selection
(EIS) criterion to improve the error-correction performance of SC-Flip
decoding. A reduction of in the implementation cost of logic elements
is estimated with the FIS approach, while simulation results show that EIS
leads to an improvement on error-correction performance improvement up to
dB at a target FER of .Comment: This version of the manuscript corrects an error in the previous
ArXiv version, as well as the published version in IEEE Xplore under the same
title, which has the DOI:10.1109/WCNCW.2018.8368991. The corrections include
all the simulations of SC-Flip-based and SC-Oracle decoders, along with
associated comments in-tex
Selective Decoding in Associative Memories Based on Sparse-Clustered Networks
Associative memories are structures that can retrieve previously stored
information given a partial input pattern instead of an explicit address as in
indexed memories. A few hardware approaches have recently been introduced for a
new family of associative memories based on Sparse-Clustered Networks (SCN)
that show attractive features. These architectures are suitable for
implementations with low retrieval latency, but are limited to small networks
that store a few hundred data entries. In this paper, a new hardware
architecture of SCNs is proposed that features a new data-storage technique as
well as a method we refer to as Selective Decoding (SD-SCN). The SD-SCN has
been implemented using a similar FPGA used in the previous efforts and achieves
two orders of magnitude higher capacity, with no error-performance penalty but
with the cost of few extra clock cycles per data access.Comment: 4 pages, Accepted in IEEE Global SIP 2013 conferenc
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