Charge Pump Clock Generation PLL for the Data Output Block of the Upgraded ATLAS Pixel Front-End in 130 nm CMOS

FE-I4 is the 130 nm ATLAS pixel IC currently under development for upgraded Large Hadron Collider (LHC) luminosities. FE-I4 is based on a low-power analog pixel array and digital architecture concepts tuned to higher hit rates [1]. An integrated Phase Locked Loop (PLL) has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40 MHz bunch crossing reference clock. This block is designed for low power, low area consumption and recovers quickly from loss of lock related to single-event transients in the high radiation environment of the ATLAS pixel detector. After a general introduction to the new FE-I4 pixel front-end chip, this work focuses on the FE-I4 output blocks and on a first PLL prototype test chip submitted in early 2009. The PLL is nominally operated from a 1.2V supply and consumes 3.84mW of DC power. Under nominal operating conditions, the control voltage settles to within 2% of its nominal value in less than 700 ns. The nominal operating frequency for the ring-oscillator based Voltage Controlled Oscillator (VCO) is fVCO = 640MHz. The last sections deal with a fabricated demonstrator that provides the option of feeding the single-ended 80MHz output clock of the PLL as a clock signal to a digital test logic block integrated on-chip. The digital logic consists of an eight bit pseudo-random binary sequence generator, an eight bit to ten bit coder and a serializer. It processes data with a speed of 160 Mbit/s. All dynamic signals are driven off-chip by custommade pseudo-LVDS drivers

Muscarinic receptor subtypes in porcine detrusor: comparison with humans and regulation by bladder augmentation

The properties of muscarinic acetylcholine receptors of porcine and human bladder detrusor were compared in radioligand binding studies using [3H]quinuclidinylbenzylate as the radioligand. The receptor affinity for the radioligand and the density of muscarinic receptors was similar in male and female pigs and in humans (Kd = 35 +/- 8 pM, Bmax = 153 +/- 30 fmol/mg protein). Atropine and subtype-selective antagonists had steep and monophasic competition curves in porcine and human detrusor with a rank order of potency of atropine >> hexahydro-sila-difenidol > or = AF-DX 116 > or = pirenzepine, indicating the presence of a homogeneous population of M2 muscarinic receptors. In female pigs bladder outflow obstruction generated by partial urethral ligation or its surgical treatment by ileum augmentation or autoaugmentation did not significantly alter expression of muscarinic receptors or of alpha2A-adrenoceptors, but the power was insufficient to exclude alterations of less than 60%. We conclude that porcine and human detrusor express muscarinic receptors of the M2 subtype; despite these qualitative similarities the use of the porcine model may be limited by large biological variance with regard to quantitative receptor expressio

Muscarinic receptor subtypes in porcine detrusor: comparison with humans and regulation by bladder augmentation

The properties of muscarinic acetylcholine receptors of porcine and human bladder detrusor were compared in radioligand binding studies using [3H]quinuclidinylbenzylate as the radioligand. The receptor affinity for the radioligand and the density of muscarinic receptors was similar in male and female pigs and in humans (Kd = 35 +/- 8 pM, Bmax = 153 +/- 30 fmol/mg protein). Atropine and subtype-selective antagonists had steep and monophasic competition curves in porcine and human detrusor with a rank order of potency of atropine >> hexahydro-sila-difenidol > or = AF-DX 116 > or = pirenzepine, indicating the presence of a homogeneous population of M2 muscarinic receptors. In female pigs bladder outflow obstruction generated by partial urethral ligation or its surgical treatment by ileum augmentation or autoaugmentation did not significantly alter expression of muscarinic receptors or of alpha2A-adrenoceptors, but the power was insufficient to exclude alterations of less than 60%. We conclude that porcine and human detrusor express muscarinic receptors of the M2 subtype; despite these qualitative similarities the use of the porcine model may be limited by large biological variance with regard to quantitative receptor expressio

Prototype of a gigabit data transmitter in 65 nm CMOS for DEPFET pixel detectors at Belle-II

This paper describes the recent development of a gigabit data transmitter for the Belle-II pixel detector (PXD). The PXD is an innermost detector currently under development for the upgraded KEK-B factory in Japan. The PXD consists of two layers of DEPFET sensor modules located at 1.8 and 2.2 cm radii. Each module is equipped with three different ASIC types mounted on the detector substrate with a flip-chip technique: (a) SWITCHER for generating steering signals for the DEPFET sensors, (b) DCD for digitizing the signal currents, and (c) DHP for performing data processing and sending the data off the module to the back-end data handling hybrid via 40 cm Kapton flex and 12–15 m twisted pair (TWP) cables. To meet the requirements of the PXD data transmission, a prototype of the DHP data transmitter has been developed in a 65-nm standard CMOS technology. The transmitter test chip consists of current-mode logic (CML) drivers and a phase-locked loop (PLL) which generates a clock signal for a 1.6 Gbit/s output data stream from an 80 cm reference clock. A programmable pre-emphasis circuit is also implemented in the CML driver to compensate signal losses in the long cable by shaping the transmitted pulse response. The jitter performance was measured as 25 ps (1s distribution) by connecting the chip with 38 cm flex and 10 m TWP cables