Mesenchymal Stem Cell Therapy Regenerates the Native Bone-Tendon Junction after Surgical Repair in a Degenerative Rat Model

BACKGROUND: The enthesis, which attaches the tendon to the bone, naturally disappears with aging, thus limiting joint mobility. Surgery is frequently needed but the clinical outcome is often poor due to the decreased natural healing capacity of the elderly. This study explored the benefits of a treatment based on injecting chondrocyte and mesenchymal stem cells (MSC) in a new rat model of degenerative enthesis repair. METHODOLOGY: The Achilles' tendon was cut and the enthesis destroyed. The damage was repaired by classical surgery without cell injection (group G1, n = 52) and with chondrocyte (group G2, n = 51) or MSC injection (group G3, n = 39). The healing rate was determined macroscopically 15, 30 and 45 days later. The production and organization of a new enthesis was assessed by histological scoring of collagen II immunostaining, glycoaminoglycan production and the presence of columnar chondrocytes. The biomechanical load required to rupture the bone-tendon junction was determined. PRINCIPAL FINDINGS: The spontaneous healing rate in the G1 control group was 40%, close to those observed in humans. Cell injection significantly improved healing (69%, p = 0.0028 for G2 and p = 0.006 for G3) and the load-to-failure after 45 days (p<0.05) over controls. A new enthesis was clearly produced in cell-injected G2 and G3 rats, but not in the controls. Only the MSC-injected G3 rats had an organized enthesis with columnar chondrocytes as in a native enthesis 45 days after surgery. CONCLUSIONS: Cell therapy is an efficient procedure for reconstructing degenerative entheses. MSC treatment produced better organ regeneration than chondrocyte treatment. The morphological and biomechanical properties were similar to those of a native enthesis

CMOS blocks for ultra-low-power sensing systems

For a few years now, everything has been getting “green”. Reduction of the ecological footprint has become a public fad and buzzwords such as green industry and green transportation have entered into the everyday language. Electronics is no exception to the rule. Ultra-low-power (ULP) design of integrated circuits has spread out during the last decade, leading to exciting research topics, among which emerging applications such as sensor networks or RFID tags. Those applications generally feature a low data throughput which easily allows for targeting a reduction of the power consumption. Ultimately, this could give rise to new application trends based on energy-autonomous systems (EAS) which however did not reach their full potential yet. Indeed, many applications such as body-implanted or infrastructure-integrated micro sensors require their autonomy to reach over 10 to 100 years while being miniaturized. A limitation comes from the fact that battery density did not follow this miniaturization trend, pushing ahead the need for highly efficient energy scavenging sources and integrated circuits in order for the incident and consumed powers to match. Given the very low activity of such systems, power consumption may be dominated by static leakage. Therefore, along with an appropriate technology choice and without compromising the functional performance, specific disruptive ultra-low-leakage design techniques for drastically reducing the off-current in CMOS mixed analog-digital microsystems must be developed. This thesis contributes to the development of low-cost energy-autonomous systems by proposing design methodologies and techniques together with fully CMOS compatible dedicated blocks. We focus more particularly here on the analog circuit blocks: AC/DC power converters for environmental energy scavenging, hybrid analog-digital LDO for power management and ultra-low-power sensor interface. Altogether, we demonstrate the feasibility of designing the transponder of a sensor node with a power consumption that remains below 10µW while preserving performances.(FSA - Sciences de l'ingénieur) -- UCL, 201

Fully-Automated and Portable Design Methodology for Optimal Sizing of Energy-Efficient CMOS Voltage Rectifiers

This paper presents a specific, fully-automated and portable design methodology used to optimize implementations of AC–DC rectifiers using MOS diodes. Output voltage and efficiency are theoretically analyzed taking into account influences of devices DC and AC characteristics, input signal voltages and frequencies as well as load currents, temperatures, backgate voltages and even capacitors and diodes parasitic capacitances. An experimental voltage multiplier is designed in a 1 $mu$ m multiple-threshold voltage SOI CMOS technology for ultra low power applications at 13.56 MHz

A modified gm/ID design methodology for deeply scaled CMOS technologies

This paper presents an updated version of the gm/ID-based sizing methodology for advanced short-channel CMOS technologies. The objective of this technique is to quickly and accurately size any linear analog circuit, top–down, from some required specifications and evaluate the remaining ones. A database describing the underlying MOS technology is taken as input of the sizing script, making the sizing process technology and corner independent. An advanced CMOS technology is analyzed, underlining the limitations of the original gm/ID methodology and its past improvements, then the proposed methodology is described in detail and tested successfully on a double stage amplifier, using two different CMOS technologies in all process-voltage-temperature corners

Design of an Ultra-Low-Power multi-stage AC/DC voltage rectifier and multiplier using a fully-automated and portable design methodology

A fully-automated and portable design methodology has been developed based on an efficient model and a gradient's method to optimize an ULP (Ultra Low Power) AC-DC multi-stage rectifier through the overall design window in a practical design time. Innovative ULP diodes featuring two CMOS transistors are modeled and used to reduce leakage. The diode model includes parasitic capacitances, thus taking into account DC and AC behavior for various frequencies and voltage amplitudes. A 3-stage rectifier taking a 1 Vpp input sinusoidal signal at 13.56 MHz and providing a 10 μA load current has been designed in 250 nm bulk CMOS technology with 72% power conversion efficiency and 1.99 V output voltage. Robust design decisions with respect to process corner variations have been reached with this methodology and are also presented

Network architecture for wirelessly interfacing sensors at ultra low power

A sensing network is described, consisting of a multiplexing reader and one or more sensor pairs, each sensor pair comprising a transponder and a dedicated reader, dedicated to that transponder, each transponder having a sensor. Each sensor pair is able to wirelessly interface and power both capacitive and resistive sensors at a short distance with high efficiency. By providing a dedicated reader for each transponder, each link can be optimized and there is no need for the dedicated reader to distinguish between signals from other transponders. The transponder generates an analog signal directly using a sensor or analog memory value and sends it by modulation to the dedicated reader. So, the dedicated readers do not need to have circuitry to demodulate a digital signal or ID code. The transponder includes the sensors and their electronic circuits and can be optionally remotely powered by the dedicated reader through the wireless link. The expected consumption of the dedicated reader can be lower than 200 μW

Automated Design of a 13.56 MHz 19µW Passive Rectifier With 72% Efficiency Under 10µA load

A three-stage Greinacher rectifier is designed using ultra-low-leakage CMOS diodes and characterized at 13.56 MHz for a 1 Vpp sinusoidal input and a 10 μA load current in 250 nm CMOS bulk technology. The measured dc output voltage is 1.9 V with 72% power conversion efficiency providing a 19 μW output power. This ultra-low-power and high-efficiency ac/dc power converter with 0.13 mm2 chip area can be used with RF energy harvesters to power implantable or wearable biomedical devices in body sensor networks. The automated design optimization methodology using a gradient method and foundry models is presented and discussed. The measured performances are presented for various frequencies, load currents, and input voltages. The robustness against process and temperature variations is studied through temperature measurements and corner simulations

Very high efficiency 13.56 MHz RFID input stage voltage multipliers based on ultra low power MOS diodes

This paper presents an ULP (ultra-low-power) diode based voltage multiplier which is used to convert RF input signal to DC supply voltage. This uses an input signal of 1 V peak to peak and 13.56 MHz frequency and reaches 2 to 3 V at its output with 10 diodes. The IC is implemented in a 2 mu m multiple- threshold voltage SOI CMOS technology. The IC outperforms, by a factor larger than 2, classical MOS diodes based voltage multiplier, implemented on the same technology, from the point of view of efficiency (minimum RF input power for given output specifications) and impedance.Anglai

A self-tuning inductive powering system for biomedical implants

This paper describes the design and implementation of a self-tuning inductive powering system conceived for biomedical applications. The circuit operates at 1 MHz and delivers 380 mW to the implant with an efficiency of 50%, at a distance of 1 cm. Absorption modulation is used to monitor the circuit parameters allowing the system to deal with distance increases up to 5 cm as well as small coil misalignments. The automatic-tuning system adjusts the configuration of the coil driver depending on the self-monitored coupling, acting on a bank of switchable capacitors with a pattern defined by the received data. It is demonstrated that the implemented tuning strategy boosts the transmitted power by a factor two. In addition, the combination of tuning and smart power regulation was proven to sensibly increase the system efficiency by maintaining a constant energy level at the secondary