A protocol and memory manager for on-chip communication

We define a protocol for on-chip communication that supports dynamic interconnect networks with global memory management based on the notion of distributed shared memory with a uniform address space. The protocol is implemented by a memory manager. It is beneficial to separate the steady-state processing (data communication with static interconnect) from changing from one steady state (or user function) to another, which may necessitate reallocation of resources or changes in the network topology

Procesing system and method for transmiting data.

A method for exchanging data between a first and a second functional unit is described, which comprises the following steps: in a first handshake procedure, data is exchanged corresponding to a communication thread (TID) selected by the first functional unit (I), while independently in a second handshake procedure, information relating to a status of at least one communication thread is exchanged from the second (T) to the first functional unit (I). The information enables the first functional unit (I) to anticipate the possibility of exchanging data for the at least one communication thread

Integrated circuit and method for buffering to optimize burst length in networks on chips.

An integrated circuit comprising a plurality of processing modules (M, S) coupled by an interconnect means (N) is provided. A first processing module (M) communicates with a second processing module (S) based on transactions. A first wrapper means (WM 1 ) associated to said second processing module (S) buffers data from said second processing module (S) to be transferred over said interconnect means until a first amount of data is buffered and then transfers said first amount of buffered data to said first processing module (M)

A network-on-chip monitoring infrastructure for communication-centric debug of embedded multi-processor SoCs

\u3cp\u3eProblems in a new System on Chip (SOC) consisting of hardware and embedded software often only show up when a silicon prototype of the chip is placed in its intended target environment and the application is executed. Traditionally, the debugging of embedded systems is difficult and time consuming because of the intrinsic lack of internal system observability and controlability in the target environment. Design for Debug (DfD) is the act of adding debug support to the design of a chip, in the realization that not every SOC is correct first time. DfD provides debug engineers with increased observability and controlability of the internal operation of an embedded system. In this paper, we present a monitoring infrastructure for multi-processor SOCs with a Network on Chip (NOC), and explain its application to performance analysis and debug. We describe how our monitors aid in the performance analysis and debug of the interactions of the embedded processors. We present a generic template for bus and router monitors, and show how they are instantiated at design time in our NOC design flow. We conclude this paper with details of their hardware cost.\u3c/p\u3

Enhancing the security of time-division-multiplexing networks-on-chip through the use of multipath routing

\u3cp\u3eAfter gaining popularity as a method of authentication in the form of smart cards, electronic security mechanisms are making their way into the domain of embedded domain with the goal of protecting Intellectual Property or for Digital Rights Management. A key role in implementing security at chip-level is played by the interconnect, which has the task of providing and regulating the flow of data between an increasing number of on-chip elements, not all of which can be considered trustworthy. Networks-on-Chip are emerging as a scalable solution for modern on-chip communication. In this study we aim to improve NoC security by forcing the messages to be routed on multiple disjoint paths, optionally in a non-deterministic manner. We implement our proposal and find it to have a reasonably low cost in terms of hardware area, although potentially having a larger overhead in terms of allocated bandwidth.\u3c/p\u3

Integrated circuit and method of arbitration in a network on an integrated circuit.

The invention relates to an integrated circuit and to a method of arbitration in a network on an integrated circuit. According to the invention, a method of arbitration in a network on an integrated circuit is provided, the network comprising a router unit, the router unit comprising a first input port, a second input port and an output port, wherein the router unit receives at least one first packet via the first input port, and wherein the router unit receives at least one second packet via the second input port, the router unit arbitrating between the first packet and the second packet, characterized in that the step of arbitrating is performed using a first label and a second label, the first label being attached to the first packet, and the second label being attached to the second packet.; This method relies on the perception that the arbitration performed by a router should be based on connection arbitration instead of input port arbitration. This means that instead of merely arbitrating between the contending input ports in a router, the arbitration should also take into account the connections to which packets correspond. This can be done by attaching labels to the packets, which labels are used in the arbitration process. In this way, it is possible to achieve a fair allocation of bandwidth to different connections, regardless of on which input ports these connections are established

Debugging multi-core systems-on-chip

In this chapter, we introduced three fundamental reasons why debugging a multi-processor SoC is intrinsically difficult; (1) limited internal observability, (2) asynchronicity, and (3) non-determinism

Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip

Networks on chip (NoC) have emerged as the design paradigm for scalable system on chip (SoC) communication infrastructure. Due to convergence, a growing number of applications are integrated on the same chip. When combined, these applications result in use-cases with different communication requirements. The NoC is configured per use-case and traditionally all running applications are disrupted during use-case transitions, even those continuing operation. In this paper we present a model that enables partial reconfiguration of NoCs and a mapping algorithm that uses the model to map multiple applications onto a NoC with undisrupted quality-of-service during reconfiguration. The performance of the methodology is verified by comparison with existing solutions for several SoC designs. We apply the algorithm to a mobile phone SoC with telecom, multimedia and gaming applications, reducing NoC area by more than 17% and power consumption by 50% compared to a state-of-the-art approac