18,560 research outputs found

    Book review: L'allevamento ecologico del coniglio (Organic rabbit farming)

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    González-Redondo, P. (2011). Book review: L'allevamento ecologico del coniglio (Organic rabbit farming). World Rabbit Science. 19(3). doi:10.4995/wrs.2011.869.SWORD19

    Motivic Milnor fiber of a quasi-ordinary hypersurface

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    Let f : (Cd+1, 0) -> (C, 0) be a germ of complex analytic function such that its zero level defines an irreducible germ of quasi-ordinary hypersurface (S, 0) subset of (Cd+1, 0). We describe the motivic Igusa zeta function, the motivic Milnor fibre and the Hodge-Steenbrink spectrum of f at 0 in terms of topological invariants of (S, 0) subset of (Cd+1, 0)

    Log canonical thresholds of quasi-ordinary hypersurface singularities

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    The log canonical thresholds of irreducible quasi-ordinary hypersurface singularities are computed, using an explicit list of pole candidates for the motivic zeta function found by the last two authors

    Using MCD-DVS for dynamic thermal management performance improvement

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    With chip temperature being a major hurdle in microprocessor design, techniques to recover the performance loss due to thermal emergency mechanisms are crucial in order to sustain performance growth. Many techniques for power reduction in the past and some on thermal management more recently have contributed to alleviate this problem. Probably the most important thermal control technique is dynamic voltage and frequency scaling (DVS) which allows for almost cubic reduction in power with worst-case performance penalty only linear. So far, DVS techniques for temperature control have been studied at the chip level. Finer grain DVS is feasible if a globally-asynchronous locally-synchronous (GALS) design style is employed. GALS, also known as multiple-clock domain (MCD), allows for an independent voltage and frequency control for each one of the clock domains that are part of the chip. There are several studies on DVS for GALS that aim to improve energy and power efficiency but not temperature. This paper proposes and analyses the usage of DVS at the domain level to control temperature in a clustered MCD microarchitecture with the goal of improving the performance of applications that do not meet the thermal constraints imposed by the designers.Peer ReviewedPostprint (published version

    Coulomb-driven flow of a dielectric liquid subject to charge injection by a sharp electrode

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    Injection of charge by a sharp electrode into a surrounding dielectric liquid leads to Coulomb forces that set the liquid into motion. An analysis is presented of this motion in a small region around the edge of the electrode, which determines the injected current as a function of the far electric potential seen by this region. By using an injection law appropriate for nonpolar liquids, the analysis predicts an electric current that increases first exponentially and then as the power 7 3 of the harmonic part of the electric potential, sometimes with a range of multiplicity in betweenMinisterio de Ciencia e Innovación PB95-0008

    Understanding the thermal implications of multicore architectures

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    Multicore architectures are becoming the main design paradigm for current and future processors. The main reason is that multicore designs provide an effective way of overcoming instruction-level parallelism (ILP) limitations by exploiting thread-level parallelism (TLP). In addition, it is a power and complexity-effective way of taking advantage of the huge number of transistors that can be integrated on a chip. On the other hand, today's higher than ever power densities have made temperature one of the main limitations of microprocessor evolution. Thermal management in multicore architectures is a fairly new area. Some works have addressed dynamic thermal management in bi/quad-core architectures. This work provides insight and explores different alternatives for thermal management in multicore architectures with 16 cores. Schemes employing both energy reduction and activity migration are explored and improvements for thread migration schemes are proposed.Peer ReviewedPostprint (published version
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