iDocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

In recent years, there has been an increasing demand to digitize and electronically access historical records. Optical character recognition (OCR) is typically applied to scanned historical archives to transcribe them from document images into machine-readable texts. Many libraries offer special stationary equipment for scanning historical documents. However, to digitize these records without removing them from where they are archived, portable devices that combine scanning and OCR capabilities are required. An existing end-to-end OCR software called anyOCR achieves high recognition accuracy for historical documents. However, it is unsuitable for portable devices, as it exhibits high computational complexity resulting in long runtime and high power consumption. Therefore, we have designed and implemented a configurable hardware-software programmable SoC called iDocChip that makes use of anyOCR techniques to achieve high accuracy. As a low-power and energy-efficient system with real-time capabilities, the iDocChip delivers the required portability. In this paper, we present the hybrid CPU-FPGA architecture of iDocChip along with the optimized software implementations of the anyOCR. We demonstrate our results on multiple platforms with respect to runtime and power consumption. The iDocChip system outperforms the existing anyOCR by 44× while achieving 2201× higher energy efficiency and a 3.8% increase in recognition accuracy

An In-DRAM Neural Network Processing Engine

Many advanced neural network inference engines are bounded by the available memory bandwidth. The conventional approach to address this issue is to employ high bandwidth memory devices or to adapt data compression techniques (reduced precision, sparse weight matrices). Alternatively, an emerging approach to bridge the memory-computation gap and to exploit extreme data parallelism is Processing in Memory (PIM). The close proximity of the computation units to the memory cells reduces the amount of external data transactions and it increases the overall energy efficiency of the memory system. In this work, we present a novel PIM based Binary Weighted Network (BWN) inference accelerator design that is inline with the commodity Dynamic Random Access Memory (DRAM) design and process. In order to exploit data parallelism and minimize energy, the proposed architecture integrates the basic BWN computation units at the output of the Primary Sense Amplifiers (PSAs) and the rest of the substantial logic near the Secondary Sense Amplifiers (SSAs). The power and area values are obtained at sub-array (SA) level using exhaustive circuit level simulations and full-custom layout. The proposed architecture results in an area overhead of 25 % compared to a commodity 8 Gb DRAM and delivers a throughput of 63.59 FPS (Frames per Second) for AlexNet. We also demonstrate that our architecture is extremely energy efficient, 7.25× higher FPS/W, as compared to previous works

Enhanced Ferroelectric and Dielectric Properties of Niobium-Doped Lead-Free Piezoceramics

Lead-free ceramics are promising candidates for replacing lead-based piezoelectric materials such as lead-zirconate-titanate (PZT) if they can compete in dielectric and ferroelectric characteristics. In this work, for lead-free piezoelectric ceramic, 0.74(Bi0.5Na0.5TiO3)-0.26(SrTiO3) (BNT-ST26) and niobium-substituted (Nb-BNT–ST26) ceramics were synthesized by solid-state reactions. The evolution of niobium substitution to the perovskite phase structure of BNT-ST26 ceramics was confirmed by X-ray diffraction (XRD) analysis and Raman spectra. Electromechanical properties of Nb-BNT-ST26 ceramics initially increased with the addition of niobium up to 0.5% and decreased with a further increase in Nb content. Temperature-dependent dielectric curves showed that the depolarization temperature (Td) decreased below room temperature because of Nb substitution. The composition with 0.5% Nb yielded a maximum bipolar strain (Smax) of 0.265% and normalized strain of d33* ~ 576 pm/V under an electric field of 4.6 kV/mm at room temperature. At this critical concentration of 0.5% Nb, maximum saturation polarization of 26 μC/cm2 was achieved. The dielectric constant with temperature peaks became more diffused and the depolarization temperature decreased with the increasing Nb content. The study concludes that Nb-doped BNT-ST26 is an excellent material for high-temperature, stable, frequency-dependent, lead-free piezoelectric devices

A Missense Variant in <i>HACE1</i> Is Associated with Intellectual Disability, Epilepsy, Spasticity, and Psychomotor Impairment in a Pakistani Kindred

Intellectual disability (ID), which affects around 2% to 3% of the population, accounts for 0.63% of the overall prevalence of neurodevelopmental disorders (NDD). ID is characterized by limitations in a person’s intellectual and adaptive functioning, and is caused by pathogenic variants in more than 1000 genes. Here, we report a rare missense variant (c.350T>C; p.(Leu117Ser)) in HACE1 segregating with NDD syndrome with clinical features including ID, epilepsy, spasticity, global developmental delay, and psychomotor impairment in two siblings of a consanguineous Pakistani kindred. HACE1 encodes a HECT domain and ankyrin repeat containing E3 ubiquitin protein ligase 1 (HACE1), which is involved in protein ubiquitination, localization, and cell division. HACE1 is also predicted to interact with several proteins that have been previously implicated in the ID phenotype in humans. The p.(Leu117Ser) variant replaces an evolutionarily conserved residue of HACE1 and is predicted to be deleterious by various in silico algorithms. Previously, eleven protein truncating variants of HACE1 have been reported in individuals with NDD. However, to our knowledge, p.(Leu117Ser) is the second missense variant in HACE1 found in an individual with NDD