Brain-Inspired Hyperdimensional Computing: How Thermal-Friendly for Edge Computing?

Brain-inspired hyperdimensional computing (HDC) is an emerging machine learning (ML) methods. It is based on large vectors of binary or bipolar symbols and a few simple mathematical operations. The promise of HDC is a highly efficient implementation for embedded systems like wearables. While fast implementations have been presented, other constraints have not been considered for edge computing. In this work, we aim at answering how thermal-friendly HDC for edge computing is. Devices like smartwatches, smart glasses, or even mobile systems have a restrictive cooling budget due to their limited volume. Although HDC operations are simple, the vectors are large, resulting in a high number of CPU operations and thus a heavy load on the entire system potentially causing temperature violations. In this work, the impact of HDC on the chip's temperature is investigated for the first time. We measure the temperature and power consumption of a commercial embedded system and compare HDC with conventional CNN. We reveal that HDC causes up to 6.8{\deg}C higher temperatures and leads to up to 47% more CPU throttling. Even when both HDC and CNN aim for the same throughput (i.e., perform a similar number of classifications per second), HDC still causes higher on-chip temperatures due to the larger power consumption.Comment: 4 pages, 3 figure

HW/SW Co-design for Reliable In-memory Brain-inspired Hyperdimensional Computing

Brain-inspired hyperdimensional computing (HDC) is continuously gaining remarkable attention. It is a promising alternative to traditional machine-learning approaches due to its ability to learn from little data, lightweight implementation, and resiliency against errors. However, HDC is overwhelmingly data-centric similar to traditional machine-learning algorithms. In-memory computing is rapidly emerging to overcome the von Neumann bottleneck by eliminating data movements between compute and storage units. In this work, we investigate and model the impact of imprecise in-memory computing hardware on the inference accuracy of HDC. Our modeling is based on 14nm FinFET technology fully calibrated with Intel measurement data. We accurately model, for the first time, the voltage-dependent error probability in SRAM-based and FeFET-based in-memory computing. Thanks to HDC's resiliency against errors, the complexity of the underlying hardware can be reduced, providing large energy savings of up to 6x. Experimental results for SRAM reveal that variability-induced errors have a probability of up to 39 percent. Despite such a high error probability, the inference accuracy is only marginally impacted. This opens doors to explore new tradeoffs. We also demonstrate that the resiliency against errors is application-dependent. In addition, we investigate the robustness of HDC against errors when the underlying in-memory hardware is realized using emerging non-volatile FeFET devices instead of mature CMOS-based SRAMs. We demonstrate that inference accuracy does remain high despite the larger error probability, while large area and power savings can be obtained. All in all, HW/SW co-design is the key for efficient yet reliable in-memory hyperdimensional computing for both conventional CMOS technology and upcoming emerging technologies.Comment: 12 pages, 16 figure

Cryogenic Embedded System to Support Quantum Computing: From 5-nm FinFET to Full Processor

Quantum computing can enable novel algorithms infeasible for classical computers. For example, new material synthesis and drug optimization could benefit if quantum computers offered more quantum bits (qubits). One obstacle for scaling up quantum computers is the connection between their cryogenic qubits at temperatures between a few millikelvin and a few kelvin (depending on qubit type) and the classical processing system on chip (SoC) at room temperature ($300 \,\mathrm{K}$). Through this connection, outside heat leaks to the qubits and can disrupt their state. Hence, moving the SoC into the cryogenic part eliminates this heat leakage. However, the cooling capacity is limited, requiring a low-power SoC, which, at the same time, has to classify qubit measurements under a tight time constraint. In this work, we explore for the first time if an off-the-shelf SoC is a plausible option for such a task. Our analysis starts with measurements of state-of-the-art 5-nm fin-shaped field-effect transistors (FinFETs) at 10 and $300 \,\mathrm{K}$. Then, we calibrate a transistor compact model and create two standard cell libraries, one for each temperature. We perform synthesis and physical layout of a RISC-V SoC at $300 \,\mathrm{K}$ and analyze its performance at $10 \,\mathrm{K}$. Our simulations show that the SoC at $10 \,\mathrm{K}$ is plausible but lacks the performance to process more than a few thousand qubits under the time constraint

Harnessing the immune system in glioblastoma.

Glioblastoma is the most common primary malignant brain tumour. Survival is poor and improved treatment options are urgently needed. Although immunotherapies have emerged as effective treatments for a number of cancers, translation of these through to brain tumours is a distinct challenge, particularly due to the blood-brain barrier and the unique immune tumour microenvironment afforded by CNS-specific cells. This review discusses the immune system within the CNS, mechanisms of immune escape employed by glioblastoma, and the immunological effects of conventional glioblastoma treatments. Novel therapies for glioblastoma that harness the immune system and their current clinical progress are outlined, including cancer vaccines, T-cell therapies and immune checkpoint modulators.N.B. is funded by Cancer Research UK. T.C. is funded by the University College London Hospitals Charity. P.M. is supported by the University College Hospital/University College London Biomedical Research Centre and the National Brain Appeal