Surface States Engineering of Metal/MoS2 Contacts Using Sulfur Treatment for Reduced Contact Resistance and Variability

Variability and lack of control in the nature of contacts between metal/MoS2 interface is a major bottleneck in the realisation of high-performance devices based on layered materials for several applications. In this letter, we report on the reduction in Schottky barrier height at metal/MoS2 interface by engineering the surface states through sulphur treatment. Electrical characteristics for back-gated MoS2 field effect transistor structures were investigated for two high work-function metal contacts Ni and Pd. Contacts on MoS2 treated with sulphur exhibited significant improvements in Ohmic nature with concomitant reduction in variability compared to those on untreated MoS2 films leading to a 2x increase in extracted mobility. X-ray Photoelectron Spectroscopy (XPS) measurements, Raman Spectroscopy and comparison of threshold voltages indicated absence of additional doping or structural changes due to sulphur treatment. The Schottky barrier heights were extracted from temperature-dependent transfer characteristics based on the thermionic current model. A reduction in barrier height of 80 and 135 meV extracted for Ni/MoS2 and Pd/MoS2 contacts respectively is hence attributed to the increase in surface states (or stronger Fermi level pinning) due to sulphur treatment. The corresponding charge neutrality levels at metal/MoS2 interface, were extracted to be 0.16 eV (0.17 eV) below the conduction band before (after) Sulphur treatment. This first report of surface states engineering in MoS2 leading to superior contacts is expected to significantly benefit the entire class of devices based on layered 2D materials.Comment: 13 pages, 5 figure

Influence of O-2 flow rate on HfO2 gate dielectrics for back-gated graphene transistors

HfO2 thin films deposited on Si substrate using electron beam evaporation, are evaluated for back-gated graphene transistors. The amount of O-2 flow rate, during vaporation is optimized for 35 nm thick HfO2 films, to achieve the best optical, chemical and electrical properties. It has been observed that with increasing oxygen flow rate, thickness of the films increased and refractive index decreased due to increase in porosity resulting from the scattering of the evaporant. The films deposited at low O-2 flow rates (1 and 3 SCCM) show better optical and compositional properties. The effects of post-deposition annealing and post-metallization annealing in forming gas ambience (FGA) on the optical and electrical properties of the films have been analyzed. The film deposited at 3 SCCM O-2 flow rate shows the best properties as measured on MOS capacitors. To evaluate the performance of device properties, back-gated bilayer graphene transistors on HfO2 films deposited at two O-2 flow rates of 3 and 20 SCCM have been fabricated and characterized. The transistor with HfO2 film deposited at 3 SCCM O-2 flow rate shows better electrical properties consistent with the observations on MOS capacitor structures. This suggests that an optimum oxygen pressure is necessary to get good quality films for high performance devices

Realizing P-FETs and Photodiodes on MoS2 through area-selective p-Doping via Vacancy Engineering.

Air-stable and area-selective doping strategies have eluded 2D materials and thus been a major bottleneck in realizing the plethora of semiconductor devices which require an built in electric field accessible from a p/n junction. Here, we demonstrate the possibility of p-doping through Vacancy Engineering, which unlike previous reports of molecular/substitutional doping is both area/dopant controllable and air-stable. Through Ar+ ions of appropriate energy and fluence bombarded on exfoliated MoS2, we demonstrate creation of sulfur vacancies that vary the S:Mo stoichiometry from 1.94 to 0.97 and hence controllably introduce p-type doping as verified using in-situ XPS and ex-situ Raman/PL measurements. FETs fabricated on Ar+ bombarded flakes show complete flip in polarity of carrier type from n-type to p-type when compared to Reference samples with the same metal contacts. Furthermore, selective Ar+ Bombardment only on contacts region shows effective hole injection with I-on/I-off>10(3). Finally p/n junctions with Ar+ bombardment performed on one half of the flake demonstrate high rectification ratio (>10(4)), forward currents (similar to 0.6 mA/cm(2)) and excellent photoresponse (I-light/I-dark similar to 10(3)) and responsivity (100-400 mu A/W)

Optimization of HfO2 films for high transconductance back gated graphene transistors

Hafnium dioxide (HfO2) films, deposited using electron beam evaporation, are optimized for high performance back-gated graphene transistors. Bilayer graphene is identified on HfO2/Si substrate using optical microscope and subsequently confirmed with Raman spectroscopy. Back-gated graphene transistor, with 32 nm thick HfO2 gate dielectric, has been fabricated with very high transconductance value of 60 mu S. From the hysteresis of the current-voltage characteristics, we estimate the trap density in HfO2 to be in the mid 10(11)/cm(2) range, comparable to SiO2

Electrical, optical, structural and chemical properties of Al2TiO5 films for high-kappa gate dielectric applications

In search of alternate gate dielectrics for electronic applications, aluminum titanate (Al2TiO5) thin films were deposited at room temperature by DC reactive magnetron sputtering and characterized for their structural, chemical, optical and dielectric properties. To realize the potentiality of these films for gate dielectric applications, we investigated the influence of annealing temperature on these properties. From X-ray photoelectron spectroscopic studies, it has been observed in the as-deposited films that the presence of Al3+ and Ti4+ oxidation states which correspond to Al2O3 and TiO2 respectively. After annealing at 400 degrees C in oxygen ambient, the binding energies of Al 2p, Ti 2p and O 1s were shifted by similar to 1 eV and it remains constant with further increase of annealing temperature from 400 to 800 degrees C. This indicates the formation of an intermediate compound of Al2O3 and TiO2. The extracted Al, Ti and O ratio was 2:1:5 which confirms the formation of Al2TiO5. XRD studies indicate that the as-deposited films were amorphous. After annealing at 400 degrees C, a diffraction peak (200) corresponds to aluminum titanate (Al2TiO5) started appearing, and its intensity increases with increase of annealing temperature. Metal-Oxide-Semiconductor (MOS) capacitors were fabricated and characterized to estimate the dielectric properties of the films. The as-deposited films shows high dielectric constant (kappa = 27.0 at 100 kHz) and high leakage current density values (J= 0.33 A/cm(2) at 1 MV/cm), high oxide traps (5.5x10(13) cm(-2)) and high interface state density (1.5x10(13) cm(-2) eV(-1)). After annealing the films show improved dielectric constant and leakage current density values. The films annealed at 600 degrees C in oxygen ambient show better dielectric constant (kappa = 11.2 at 100 kHz) and leakage current density values (J= 2.23x10(-9) A/cm(2) at 1 MV/cm), low oxide traps (1.4x10(12) cm(-2)) and low interface state density (7.1x10(11) cm(-2) eV(-1)) compared with the other films. This suggests that the optimum annealing temperature is required to achieve better device properties

A sub-thermionic MoS2 FET with tunable transport

The inability to scale supply voltage and hence reduce power consumption remains a serious challenge in modern nanotransistors. This arises primarily because the Sub-threshold Swing (SS) of the thermionic MOSFET, a measure of its switching efficiency, is restricted by the Boltzmann limit (k(B)T/q = 60 mV/dec at 300 K). Tunneling FETs, the most promising candidates to circumvent this limit, employ band-to-band tunneling, yielding very low OFF currents and steep SS but at the expense of severely degraded ON currents. In a completely different approach, by introducing concurrent tuning of thermionic and tunneling components through metal/semiconductor Schottky junctions, we achieve an amalgamation of steep SS and high ON currents in the same device. We demonstrate sub-thermionic transport sustained up to 4 decades with SSmin similar to 8.3 mV/dec and SSavg similar to 37.5(25) mV/dec for 4(3) dec in few layer MoS2 dual gated FETs (planar and CMOS compatible) using tunnel injected Schottky contacts for a highly scaled drain voltage of 10 mV, the lowest for any sub-thermionic devices. Furthermore, the same devices can be tuned to operate in the thermionic regime with a field effect mobility of similar to 84.3 cm(2) V-1 s(-1). A detailed mechanism involving the independent control of the Schottky barrier height and width through efficient device architecture and material processing elucidates the functioning of these devices. The Gate Tunable Thermionic Tunnel FET can function at a supply voltage of as low as 0.5 V, reducing power consumption dramatically. Published by AIP Publishing

High-Performance HfO2 Back Gated Multilayer MoS2 Transistors

A new substrate (similar to 30-nm HfO2/Si) is developed for high-performance back-gated molybdenum disulfide (MoS2) transistors. Record drain current I-ds similar to 180 mu A/mu m and transconductance value g(m) similar to 75 mu S/mu m at V-ds = 1 V have been achieved for 1-mu m channel length multilayer MoS2 transistors on HfO2/Si substrate. The transistors on HfO2 substrate show >2.5x enhancement in field effect mobility (mu(FE) similar to 65 cm(2)/V . s) compared with the transistors on SiO2 (mu(FE) similar to 25 cm(2)/V . s) substrate. The intrinsic mobility extracted from Y function technique (mu(FE) similar to 154 cm(2)/V . s) is 3x more than SiO2 substrate. The drastic improvement in transistor performance is attributed to a combination of three factors: 1) efficient gate coupling with an EOT of 6.2 nm; 2) charge impurity screening due to high-k dielectric; and 3) very low contact resistance through sulfur treatment

Interface states reduction in atomic layer deposited TiN/ZrO2/Al2O3/Ge gate stacks

In this work, the authors report the application and influence of slot plane antenna plasma oxidation (SPAO) on the quality of Ge/high-k based metal-oxide-semiconductor capacitors. The effect of SPAO exposure on the Ge/high-k interface during atomic layer deposition of the dielectric along with the reliability characteristics has been studied. A significant improvement in the electrical properties has been observed when the high-k stacks are exposed to SPAO treatment. The devices treated with SPAO after Al2O3/ZrO2 deposition (CASE-1) show slightly better equivalent oxide thickness, low leakage current density, and marginally better breakdown characteristics compared to the devices treated with SPAO in-between Al2O3/ZrO2 deposition (CASE-2). This can be attributed to the densification of the gate stack as the plasma exposed to the total stack and the formation of the thick interfacial layer as evident from the X-ray photoelectron spectroscopy (XPS) measurements. A stable and thin interfacial layer formation was observed from XPS data in the samples treated with SPAO in-between high-k stack deposition compared to the samples treated with SPAO after high-k stack deposition. This leads to the low interface state density, low hysteresis, comparable dielectric breakdown, and reliable characteristics in CASE-2 compared to CASE-1. On the other hand, XPS data revealed that the interface is deteriorated in the samples treated with SPAO before high-k stack deposition (CASE-3) and leads to poor electrical properties. Published by the AVS

Intrinsic Limit for Contact Resistance in Exfoliated Multilayered MoS2 FET

A new method for the separation of contact resistance (R-contact) into Schottky barrier resistance (R-SB) and interlayer resistance (R-IL) is proposed for multilayered MoS2 FETs. While R-SB varies exponentially with Schottky barrier height (Phi(bn)), R-IL essentially remains unchanged. An empirical model utilizing this dependence of R-contact versus Phi(bn) is proposed and fits to the experimental data. The results, on comparison with the existing reports of lowest R-contact, suggest that the extracted R-IL (1.53 k Omega.mu m) for an unaltered channel would determine the lower limit of intrinsic R-contact even for barrierless contacts for multilayered exfoliated MoS2 FETs