Lattice matched GaN/InAlN waveguides at λ = 1.55 μm grown by metalorganic vapor phase epitaxy

We report on the demonstration of low-loss, single-mode GaN-InAlN ridge waveguides (WGs) at fiber-optics telecommunication wavelengths. The structure grown by metal-organic vapor phase epitaxy contains AlInN cladding layers lattice-matched to GaN. For slab-like WGs propagation losses are below 3 dB/mm and independent of light polarization. For 2.6-μm-wide WGs the propagation losses in the 1.5- to 1.58-μm spectral region are as low as 1.8 and 4.9 dB/mm for transverse-electric- and transverse-magnetic-polarization, respectively. The losses are attributed to the sidewall roughness and can be further reduced by the optimization of the etching process

Effect of Gate Field-Plate Geometry on On-Resistance in AlGan/GaN HEMTs for Power Applications

On-resistance (RDSon) degradation is a well-known issue in AlGaN/GaN HEMTs technology for power applications [1,2], and is usually observed when the device is rapidly switched from off- to on-state condition. The introduction of field-plate terminals has proven to be a viable solution in order to mitigate the off-state electric fields and consequently improve the dynamic on-resistance behavior [2]. In this work the effect of different field-plate geometry will be investigated. Moreover, by using different characterization techniques, some insights on the trapping mechanisms causing the RDSon degradation will also be presented

MOCVD of HfO2 and ZrO2 high-k gate dielectrics for InAlN/AlN/GaN MOS-HEMTs

We apply metal organic chemical vapour deposition (MOCVD) of HfO2 and of ZrO2 from beta-diketonate precursors to grow high-k gate dielectrics for InAlN/AlN/GaN metal oxide semiconductor (MOS)-high electron mobility transistors (HEMTs). High-k oxides of about 12 nm-14 nm are deposited for the MOS-HEMTs incorporating Ni/Au gates, whereas as a reference, Ni-contact-based 'conventional' Schottky-barrier (SB)-HEMTs are processed. The processed dielectrics decrease the gate current leakage of the HEMTs by about four orders of magnitude if compared with the SB-gated HEMTs and show superior device characteristics in terms of I-DS and breakdown

Thermally induced voltage shift in capacitance-voltage characteristics and its relation to oxide/semiconductor interface states in Ni/Al2O3/InAlN/GaN heterostructures

The Ni/Al2O3/InAlN/AlN/GaN metal-oxide-semiconductor heterostructure (MOS-H) is investigated using capacitance-voltage and capacitance-time characteristics in the temperature range of 25-300 degrees C. An anomalous positive voltage shift of the capacitance-voltage curve with increasing temperature was observed and attributed to the hole emission from the oxide/semiconductor interface states. Distribution of the interface states density, Dit(E), at the Al2O3/InAlN interface was evaluated using a modification of the constant-capacitance deep-level transient spectroscopy. The MOS-H capacitor threshold voltage shift under negative bias was repetitively recorded as a function of time at elevated temperatures. Dit in the range of 0.1-3 x 10(13) eV(-1) cm(-2) was determined

Threshold Voltage Instabilities in D-Mode GaN HEMTs for Power Switching Applications

Threshold voltage instabilities observed in GaN HEMTs designed for power switching applications when submitted to either DC or pulsed testing are here presented and interpreted. Main results can be summarized as follows: i) two acceptor trap levels, characterized by two well distinct time constants, are present in the UID GaN channel and C-doped GaN buffer respectively and behave as electron and hole traps respectively; ii) the trapped charge is modulated by the high voltage biasing of the gate and drain terminals; iii) when empty, channel electron traps induce a negative threshold-voltage shift, while buffer hole traps induce a positive threshold-voltage shift; iv) when the device is pulsed from off-to on-state conditions, trap charge/discharge dynamics induces negative and positive threshold-voltage instabilities over distinct time scales

Current transport and barrier height evaluation in Ni/InAlN/GaN Schottky diodes

The current-voltage characteristics of the Ni/InAlN/GaN Schottky diodes were measured at various temperatures in the range of 300-700 K. The experimental data were analyzed considering different current-transport mechanisms. From the analysis it follows that the tunneling current, which might be due to a multistep tunneling along dislocations, is the dominant component at all temperatures in the samples investigated. The barrier height of the Ni/InAlN/GaN Schottky diodes, evaluated from the thermionic emission current, shows a slightly negative temperature coefficient and its value at 300 K is >= 1.46 eV. This is significantly higher barrier height than reported before (<1 eV). This discrepancy follows from an incorrect evaluation using the intercept and slope of a measured characteristic without separation of the individual current components. (C) 2010 American Institute of Physics. [doi:10.1063/1.3442486

Analysis of degradation mechanisms in lattice-matched InAlN/GaN high-electron-mobility transistors

We address degradation aspects of lattice-matched unpassivated InAlN/GaN high-electron-mobility transistors (HEMTs). Stress conditions include an off-state stress, a semi-on stress (with a partially opened channel), and a negative gate bias stress (with source and drain contacts grounded). Degradation is analyzed by measuring the drain current, a threshold voltage, a Schottky contact barrier height, a gate leakage and an ideality factor, an access, and an intrinsic channel resistance, respectively. For the drain-gate bias < 38 V parameters are only reversibly degraded due to charging of the pre-existing surface states. This is in a clear contrast to reported AlGaN/GaN HEMTs where an irreversible damage and a lattice relaxation have been found for similar conditions. For drain-gate biases over 38 V InAlN/GaN HEMTs show again only temporal changes for the negative gate bias stresses; however, irreversible damage was found for the off-state and for the semi-on stresses. Most severe changes, an increase in the intrinsic channel resistance by one order of magnitude and a decrease in the drain current by similar to 70%, are found after the off-state similar to 50 V drain-gate bias stresses. We conclude that in the off-state condition hot electrons may create defects or ionize deep states in the GaN buffer or at the InAlN/GaN interface. If an InAlN/GaN HEMT channel is opened during the stress, lack of the strain in the barrier layer is beneficial for enhancing the device stability